Techniques and mechanisms for regulating a temperature of a resonator structure. In an embodiment, a thermoelectric cooler (TEC) is thermally coupled to a resonator which is proximate thereto. The resonator supports operation with an oscillator circuit, wherein a resonance characteristic of the resonator contributes to oscillations of a master clock signal, or other oscillatory signal, which is provided with the oscillator circuit. The TEC provides Peltier functionality to selectively perform either one of heating or cooling the resonator. In another embodiment, the TEC is configured to conduct heat which is transferred via a path between the TEC and the resonator, wherein the path omits any circuitry which is to perform operations which are synchronized based on the oscillatory signal.

A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

A semiconductor device including a package, a lid and a thermal interface material is provided. The package includes a packaging substrate, semiconductor dies and an insulating encapsulation, wherein the semiconductor dies are disposed on and electrically connected to the packaging substrate, and the insulating encapsulation encapsulates the semiconductor dies. The lid is disposed on the packaging substrate, the lid includes a cover portion and foot portion extending from the cover portion to the packaging substrate, wherein the cover portion covers the semiconductor dies and the insulating encapsulation, the foot portion includes foot segments laterally spaced apart from one another, and the foot segments are attached to the packaging substrate. The cover portion of the lid is attached to the package through the thermal interface material.

A semiconductor package includes a wiring board including at least one pair of connection structures electrically connecting at least one pair of differential signal transmission lines and at least one pair of differential signal transmission terminals, respectively. The at least one pair of connection structures includes first via structures staggered in a vertical direction, at least one first connection line electrically connecting the first via structures, second via structures staggered in the vertical direction, and at least one second connection line electrically connecting the second via structures. The at least one first connection line is spaced apart from the at least one second connection line in the vertical direction and electrically insulated therefrom, and intersects the at least one second connection line in the vertical direction.

A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

A semiconductor device has a substrate and a first semiconductor die disposed over the substrate. A subpackage is also disposed over the substrate. A stiffener is disposed over the substrate around the first semiconductor die and subpackage. A heat spreader is disposed over the stiffener. The heat spreader is thermally coupled to the first semiconductor die. The heat spreader has an opening over the subpackage.

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.

A semiconductor package including a substrate and at least one semiconductor chip on the substrate may be provided. The substrate may include a body layer having a top surface and a bottom surface, a first thermal conductive plate on the top surface of the body layer, the first thermal conductive plate connected to a ground terminal of the semiconductor chip, and a thermal conductive via penetrating the body layer and being in contact with the first thermal conductive plate.

A semiconductor device includes a substrate, an electronic component, a cover and a liquid metal. The electronic component is disposed on the substrate. The cover is disposed on the substrate and covers the electronic component. The liquid metal is formed between the cover and the electronic component.