A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the leadframe, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.

In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.

A semiconductor package device having a porous copper adhesion promoter layer is provided. The porous copper adhesion promoter layer developed via de-metallization of the intermetallic compound layer grown after the thermal treatment of a thin metal layer plated on the copper base material. The highly selective de-metallization of the intermetallic compound layer ensures that the plated surfaces are not affected and does not create wire-bondability issues. The porous copper layer solves the delamination between the carrier and the epoxy molding compound by providing mechanical interlock features. Further, increasing the surface area of contact between the carrier and the epoxy molding compound improves the mechanical interlock features.

A module includes a substrate including a first surface, at least one first component mounted on the first surface, a shield member mounted on the first surface to cover the first component, and a first sealing resin arranged at least between the shield member and the first surface. The shield member includes a top surface portion in a form of a plate and a plurality of leg portions that extend from the top surface portion toward the first surface.

A semiconductor device of embodiments includes: a die pad including a first region and a second region surrounding the first region and thinner than the first region; a semiconductor chip including an upper electrode, a lower electrode, and a silicon carbide layer between the upper electrode and the lower electrode and provided on an inner side rather than the second region on a surface of the die pad; and a connection layer for connecting the lower electrode to the surface.

An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.

A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface.

Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.

A semiconductor package includes a semiconductor chip on a package substrate, a dam structure disposed on the package substrate and surrounding the semiconductor chip, the dam structure including a first dam portion having a first length in a vertical direction, and a second dam portion connected to the first dam portion and extending from an outer side of the first dam portion, and having a second length less than the first length in the vertical direction, and an adhesive layer disposed on the package substrate, the adhesive layer including a first adhesive portion disposed between the semiconductor chip and the package substrate and overlapping the semiconductor chip in the vertical direction, and a second adhesive portion on an outer side of the semiconductor chip and including at least a part contacting a top surface of the first dam portion.

A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.