A semiconductor die and an electrically conductive ribbon are arranged on a substrate. The electrically conductive ribbon includes a roughened surface. An insulating encapsulation is molded onto the semiconductor die and the electrically conductive ribbon. The roughened surface of the electrically conductive ribbon provides a roughened coupling interface to the insulating encapsulation.

A semiconductor package includes a first redistribution structure including a plurality of first redistribution layers and a plurality of first redistribution vias. A semiconductor chip is on the first redistribution structure. The semiconductor chip includes a chip pad. A connection pad is between the first redistribution structure and the semiconductor chip, and is connected to the first redistribution structure. A connection bump is connected to the connection pad and the chip pad. A molding layer extends around the first redistribution structure and the semiconductor chip, and a through electrode extends through the molding layer. A wetting layer is between the first redistribution structure and the molding layer.

A light-emitting device includes a carrier, a light-emitting element and a connection structure. The carrier includes a first electrical conduction portion. The light-emitting element includes a first light-emitting layer capable of emitting first light and a first contact electrode formed under the light-emitting layer. The first contact electrode is corresponded to the first electrical conduction portion. The connection structure includes a first electrical connection portion and a protective portion surrounding the first contact electrode and the first electrical connection portion. The first electrical connection portion includes an upper portion, a lower portion and a neck portion arranged between the upper portion and the lower portion. An edge of the upper portion is protruded beyond the neck portion, and an edge of the lower portion is protruded beyond the upper portion.

This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area.

Embossed solder masks for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a package substrate includes the solder mask with non-planar features along a surface of the solder mask such that the area of the surface is increased. The non-planar features may correspond to concave recesses formed on the surface of the solder mask. Physical dimensions (e.g., widths, depths) and/or areal densities of the non-planar features of the embossed solder masks may vary based on local areas of the package substrate exclusive of conductive bumps. The non-planar features may be formed by pressing a mold having convex features against the surface of the solder mask. The solder mask may be heated while pressing the mold against the surface of the solder mask. In some embodiments, the mold includes regions lacking the convex features.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

A semiconductor device, including a substrate having a mounting area on a front surface thereof, a semiconductor chip disposed in the mounting area, and an exterior member having a bottom surface bonded to the front surface of the substrate, the exterior member continuously surrounding the mounting area in a loop shape in a plan view of the semiconductor device, to thereby enclose a housing space, the mounting area being in the housing space. The semiconductor device further includes a sealing material sealing the housing space.

A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.

A power module includes a power semiconductor element, an interconnection material, a circuit board, an external terminal, a joining material, and a sealing resin. A clearance portion is continuously formed between the sealing resin and each of an end surface of the joining material and a surface of the interconnection material so as to extend from the end surface of the joining material to the surface of the interconnection material, the end surface of the joining material being located between the power semiconductor element and the interconnection material, the surface of the interconnection material being located between the end surface and a predetermined position of the interconnection material separated by a distance from the end surface.