An example embodiment relates to a radiofrequency (RF) power amplifier pallet, and further relates to an electronic device that includes such a pallet. The RF power amplifier pallet may include a coupled line coupler that includes a first line segment and a second line segment that is electromagnetically coupled to the first line segment. A first end of the first line segment may be electrically connected to an output of an RF amplifying unit. The RF power amplifier pallet may further include a dielectric filled waveguide having an end section of the first dielectric substrate, an end section of the second dielectric substrate, and a plurality of metal wall segments covering the end sections of the first and second dielectric layers. The plurality of metal wall segments may be arranged spaced apart from the first line segment and electrically connected to a first end of the second line segment.

An electronic device has a plurality of integrated circuits fixed to a support between transmitting and receiving antennas. An integrated circuit generates a synchronization signal supplied to the other integrated circuits. Each integrated circuit is formed in a die integrating electronic components and overlaid by a connection region according to the Flip-Chip Ball-Grid-array or embedded Wafer Level BGA. A plurality of solder balls for each integrated circuit is electrically coupled to the electronic components and bonded between the respective integrated circuit and the support. The solder balls are arranged in an array, aligned along a plurality of lines parallel to a direction, wherein the plurality of lines comprises an empty line along which no solder balls are present. A conductive synchronization path is formed on the support and extends along the empty line of at least one integrated circuit, between the solder balls of the latter.

An integrated circuit includes a semiconductor substrate, electronic components integrated in the semiconductor substrate, an electric connection structure overlying the semiconductor substrate, and an conductive region, with elongated shaped, having a first and a second end. The conductive region is formed in the electric connection structure, extends over an entire length of the substrate and is not directly electrically connected to the electronic components. A first and a second synchronization connection element are electrically coupled to the first end and to the second end, respectively, of the conductive region and have each a respective synchronization connection portion facing the coupling face.

A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

A radio-frequency (RF) apparatus that reduces signal reflections at input and output terminals includes a semiconductor chip mounted on an assembly base upside down. The semiconductor chip includes first to third metal layers and a top metal layer that provides a top ground layer and a pad. The pad is connected to the input or output terminals on the assembly base and extracts a signal line and a stub line in the third metal layer. The semiconductor chip further includes an inner ground layer formed in the second metal layer. The inner ground layer and the signal line pulled out from the pad and formed in the third metal layer form a micro-strip line.

A microwave antenna apparatus comprises a semiconductor package module comprising a mold layer, a semiconductor element, a coupling element and a redistribution layer, and an antenna module mounted on top of the semiconductor package module, said antenna module comprising an antenna substrate, one or more antenna elements, an antenna feed layer and an antenna ground layer. The footprint of the antenna module is larger than the footprint of the semiconductor package module.

An antenna structure includes a radiative antenna element disposed in a first conductive layer, a reflector ground plane disposed in a second conductive layer under the first conductive layer, a feeding network comprising a transmission line disposed in a third conductive layer under the second conductive layer, and at least one coupling element disposed in proximity to a feeding terminal that electrically couples one end of the transmission line to the radiative antenna element. The coupling element is capacitively coupled with the feeding terminal.

Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

A semiconductor device comprises a first semiconductor chip, a first planar waveguide transmission line arranged within a BEOL metal stack of the first semiconductor chip, wherein the first planar waveguide transmission line comprises line sections situated opposite one another, and a second planar waveguide transmission line arranged over the first semiconductor chip and electrically coupled to the first planar waveguide transmission line, wherein the second planar waveguide transmission line comprises line sections situated opposite one another.

A method of forming a semiconductor structure is provided. A first inter-level dielectric (ILD) layer is formed overlying a molding layer. The first ILD layer is patterned to form a plurality of first openings. A first lower transmitter electrode and a first lower receiver electrode are formed by depositing a first metal material within the plurality of first openings. A first dielectric waveguide is formed overlying the first ILD layer, the first lower transmitter electrode and the first lower receiver electrode. A second ILD layer is formed overlying the first dielectric waveguide and includes a plurality of second openings. A second lower transmitter electrode and a second lower receiver electrode are formed by depositing a second metal material within the plurality of second openings. A second dielectric waveguide is formed overlying the second ILD layer, the second lower transmitter electrode and the second lower receiver electrode.