INTEGRATED CIRCUIT AND ELECTRONIC DEVICE COMPRISING A PLURALITY OF INTEGRATED CIRCUITS ELECTRICALLY COUPLED THROUGH A SYNCHRONIZATION SIGNAL ROUTED THROUGH THE INTEGRATED CIRCUIT

Abstract

An integrated circuit includes a semiconductor substrate, electronic components integrated in the semiconductor substrate, an electric connection structure overlying the semiconductor substrate, and an conductive region, with elongated shaped, having a first and a second end. The conductive region is formed in the electric connection structure, extends over an entire length of the substrate and is not directly electrically connected to the electronic components. A first and a second synchronization connection element are electrically coupled to the first end and to the second end, respectively, of the conductive region and have each a respective synchronization connection portion facing the coupling face.

Claims

1. An integrated circuit having a coupling face, the integrated circuit comprising: a semiconductor substrate; electronic components integrated in the semiconductor substrate; an electric connection structure overlying the semiconductor substrate; and a conductive region, with elongated shape, having a first end and a second end, the conductive region being formed in the electric connection structure, extending over an entire length of the substrate and not being directly electrically connected to the electronic components, wherein the electric connection structure includes a plurality of connection elements having respective connection portions facing the coupling face, the plurality of connection elements including a first and a second synchronization connection element, the first and the second synchronization connection elements being electrically coupled to the first end and to the second end, respectively, of the conductive region and each having a respective synchronization connection portion facing the coupling face.

2. The integrated circuit according to claim 1, comprising an insulation layer extending over the semiconductor substrate and forming a die therewith, wherein the electric connection structure comprises a dielectric region overlying the die and having a length, and the conductive region extends within the dielectric region approximately throughout the length thereof.

3. The integrated circuit according to claim 2, wherein the first and the second synchronization connection elements include a first and a second solder ball projecting from a respective end of the dielectric region and belonging to a Ball Grid Array bonding structure.

4. The integrated circuit according to claim 3, wherein the dielectric region accommodates at least one redistribution layer of an embedded Wafer Level BGA (eWLB) coupling and the conductive region is formed in the redistribution layer.

5. The integrated circuit according to claim 1, comprising an insulation layer extending over the semiconductor substrate and forming a die therewith, the conductive region extends within the insulation layer, and the first and the second synchronization connection elements include metal connection regions extending in a dielectric region overlying or at least partially surrounding the die and in selective electric contact with the respective synchronization connection portions.

6. The integrated circuit according to claim 5, wherein the connection portions of the plurality of connection elements include solder balls belonging to a Ball Grid Array connection structure forming a Flip Chip-Ball Grid Array (FC-BGA) coupling or an embedded Wafer Level BGA (eWLB) coupling.

7. The integrated circuit according to claim 5, wherein the dielectric region includes a packaging layer, the connection portions of the plurality of connection elements include a plurality of coupling pins, and the metal connection regions include wire connections, wherein the first and the second synchronization connection elements include respective synchronization wire elements coupled between a respective end of the conductive region and a respective coupling pin.

8. The integrated circuit according to claim 1, comprising: a synchronism generator circuit configured to generate a synchronization signal; and an output terminal coupled to the generation circuit, wherein the plurality of connection elements further includes a signal connection element coupled to the output terminal and having a respective signal connection portion of the plurality of connection portions.

9. The integrated circuit according to claim 1, wherein the integrated circuit is a monolithic microwave integrated circuit.

10. The integrated circuit according to claim 1, wherein the conductive region is of metal material.

11. An electronic device, comprising: a support having a support face; a plurality of integrated circuits, each integrated circuit having a coupling face coupled to the support face and including: a semiconductor substrate integrating electronic components; an electric connection structure overlying the semiconductor substrate; and a conductive region with an elongated shape, formed within the electric connection structure, the conductive region having a first end and a second end, extending over an entire length of the substrate and not directly electrically connected to the electronic components, wherein: a first integrated circuit of the plurality of integrated circuits is configured to generate a synchronization signal, and each electric connection structure includes a plurality of connection elements, the plurality of connection elements including signal connection elements, electrically coupling the electronic components to respective signal connection portions facing the respective coupling face, and the electric connection structure of at least the first integrated circuit further includes a first and a second synchronization connection element adjacent to the signal connection elements, electrically coupled to the first and the second ends, respectively, of the respective conductive region, having a respective synchronization connection portion facing the coupling face and configured to route the synchronization signal; electronic components bonded to the support face; electric connection tracks extending on the support face and electrically coupling the electronic components to the signal connection portions of the signal connection elements of each integrated circuit; and synchronization conductive track segments extending on the support face and electrically coupling the synchronization connection portions of at least the first integrated circuit to selective signal connection portions of the integrated circuits.

12. The electronic device according to claim 11, wherein the electric connection structure comprises: an insulation layer extending over the semiconductor substrate and forming therewith a die; and a dielectric region, which extends over the die and has a length, wherein the conductive region extends within the dielectric region approximately for the entire length thereof.

13. The electronic device according to claim 12, wherein the connection portions of the plurality of connection elements comprise solder balls, belonging to a Ball Grid Array connection structure.

14. The electronic device according to claim 11, wherein the electric connection structure comprises: an insulation layer extending over the semiconductor substrate and forming a die therewith; and a dielectric region overlying or at least partially surrounding the die, wherein the conductive region extends within the insulation layer, and the first and the second connection elements extend in the dielectric region.

15. The electronic device according to claim 14, wherein the plurality of connection elements includes solder balls belonging to a Ball Grid Array connection structure forming a Flip Chip-Ball Grid Array coupling or an embedded Wafer Level BGA coupling.

16. The electronic device according to claim 14, wherein the connection elements of the plurality of connection elements include wire connections, the dielectric region includes a packaging layer, the signal connection portions and the synchronization connection portions include a plurality of coupling pins, and the first and the second synchronization connection elements include respective wire elements coupled between a respective end of the conductive region and a respective coupling pin.

17. The electronic device according to claim 11, wherein: the first integrated circuit forms a master integrated circuit, the plurality of integrated circuits includes at least a first and a second slave circuit arranged on opposite sides of the master integrated circuit, the master integrated circuit includes an output terminal coupled to a respective signal connection element of the plurality of signal connection elements and configured to supply the synchronization signal, and the synchronization conductive track segments include connection portions extending on the face of the support, between the signal connection portions of the first and the second slave integrated circuits and the synchronization connection portions of the master integrated circuit and between the signal connection portion and the first synchronization connection portion of the master integrated circuit.

18. A device, comprising: a printed circuit board (PCB) having a surface; a semiconductor device package physically coupled to the surface of the PCB, the semiconductor device package including: a semiconductor substrate; electronic components integrated in the semiconductor substrate; an electric connection structure overlying the semiconductor substrate; and a conductive region, with elongated shape, having a first end and a second end, the conductive region being formed in the electric connection structure, extending over an entire length of the substrate and not being directly electrically connected to the electronic components, wherein the electric connection structure includes a plurality of connection elements having respective connection portions facing the coupling face, the plurality of connection elements including a first and a second synchronization connection element, the first and the second synchronization connection elements being electrically coupled to the first end and to the second end, respectively, of the conductive region and each having a respective synchronization connection portion facing the coupling face; a receiving antenna physically coupled to the surface of the PCB and electrically coupled to the semiconductor device package; and a transmitting antenna physically coupled to the surface of the PCB and electrically coupled to the semiconductor device package.

19. The device according to claim 18, wherein the semiconductor device package is disposed between the receiving antenna and the transmitting antenna.

20. The device according to claim 18, wherein the semiconductor device package is a monolithic microwave integrated circuit package.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0023] For a better understanding of the present disclosure, some embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein:

[0024] FIG. 1 shows the layout of an electronic device having a plurality of integrated circuits for radiofrequency applications of a known type;

[0025] FIG. 2 is a bottom perspective view of an integrated circuit configured to be bonded using the ball-grid-array technique;

[0026] FIG. 3 is a cross-section of a portion of the integrated circuit of FIG. 2, configured to be bonded using the FC-BGA technique;

[0027] FIG. 4 is a cross-section of a portion of the integrated circuit of FIG. 2, configured to be bonded using the eWLB technique;

[0028] FIG. 5 shows the layout of an electronic device having a plurality of integrated circuits, according to an embodiment;

[0029] FIG. 6 is a bottom view of the integrated circuit of FIG. 5;

[0030] FIG. 6A shows an enlarged detail of the integrated circuit of FIG. 6;

[0031] FIG. 7 is a cross-section of a portion of the integrated circuit of FIG. 5;

[0032] FIG. 8 shows the layout an electronic device having a plurality of integrated circuits according to another embodiment;

[0033] FIG. 9 is a cross-section of a portion of an integrated circuit of the electronic device of FIG. 8, taken along section line IX-IX;

[0034] FIG. 10 is a different embodiment of the integrated circuit of FIG. 9, taken along the same section line as FIG. 9;

[0035] FIG. 11 shows the layout of an electronic device having a plurality of integrated circuits according to a different embodiment;

[0036] FIG. 12 is a cross-section of a portion of an integrated circuit of the electronic device of FIG. 11, taken along section line XII-XII; and

[0037] FIG. 13 is a cross-section of a different embodiment of the integrated circuit of FIG. 12, taken along the same section line as FIG. 12.

DETAILED DESCRIPTION

[0038] FIG. 5 shows an electronic device 50 comprising a printed-circuit board, PCB 52, carrying four MMICs, for example, one Master MIMIC 53 and three Slave MMICs 54-56 (even though the number of Slave MMICs may be different). In the top plan view of FIG. 5, the MMICs 53-56 are arranged side-by-side, between a receiving antenna structure (RX antenna 60, at the top in FIG. 5) and a transmitting antenna structure (TX antenna 61, at the bottom in FIG. 5).

[0039] With reference to FIG. 7, the MMICs 53-56 comprise a semiconductor device package 57 (which, in some embodiments, may be referred to as a die 57) housing electronic components (represented schematically and designated as a whole by 58). A connection region 59 extends over the die 57. In case of the eWLB bonding technique, the connection region is formed by a dielectric layer accommodating metal connection lines 61, as described above with reference to FIG. 4. In case of the FC-BGA bonding technique, the connection region 59 is formed by a bonding support similar to the bonding support 7 of FIG. 3. Not visible in FIG. 7 are possible passivation layers, nor a possible peripheral region surrounding the die 57, in case of the eWLB bonding technique, or the underfill layer and bumps, in case of the FC-BGA bonding technique, but they may be present, as shown in FIGS. 4 and 3, respectively.

[0040] With reference once again to FIG. 5, the MMICs 53-56 are connected to the RX antenna 60 and the TX antenna 61 through surface electrical connections 63, formed as conductive tracks on the surface of the PCB 52 that carries the MMICs 53-56, in a known way. In addition, the MMICs 53-56 are mutually connected through buried connections, formed in the PCB 52, as described hereinafter, as well as through a synchronization line 64, described in detail hereinafter, which routes a synchronization signal LO, generated by the Master MMIC 53, through the electronic components 74 and supplied to the Slave MMICs 54-56 for their synchronization and amplitude balancing, in a per se known manner.

[0041] Hereinafter, to enable better understanding, the Slave MMICs 54-56 are also referred to as first, second, and third Slave MMICs 54, 55, and 56. In the embodiment shown (see, in particular, FIG. 5), the Master MMIC 53 is arranged between the first Slave MMIC 54 (located to the left) and the second Slave MMIC 55 (located to the right). Consequently, the synchronization signal LO crosses the Master MMIC 53 and the second Slave MMIC 55.

[0042] The MMICs 53-56 (see also FIGS. 6 and 7) are fixed and electrically connected to the PCB 52 through the solder ball technique, which uses solder balls 65. The solder balls 65 may be bonded either using the FC-BGA technique or using the eWLB technique described above and shown in FIGS. 3 and 4. It should be noted that hereinafter the term “balls” will be used, even though, after bonding, in general they are deformed and have a shape different from the spherical one.

[0043] As may be noted in FIG. 6, the solder balls 65 are arranged in rows and columns, identified in FIG. 6 by the letters A-Y and the numbers 1-18, respectively, but on the row J no solder balls 65 are present.

[0044] In this way, the row J defines an empty or missing row, i.e., the solder balls 65 arranged on the adjacent rows (rows K and H in FIG. 6) are arranged at a distance from each other greater than the distance between the other adjacent rows. In particular, with reference to the enlarged detail of FIG. 6A, if p denotes the pitch between adjacent rows in the array (i.e., the distance between the central points of solder balls 65 belonging to mutually adjacent rows), at the empty row the distance d is twice the pitch p (d=2p).

[0045] As represented by a dashed line in FIG. 6, the synchronization line 64 extends (on the PCB 52) in the empty row, between two rows of solder balls 65 arranged at the distance d.

[0046] With reference to FIG. 7, the PCB 52 comprises, in a known way, a body 67 of dielectric material, which has a first face 67A and a second face 67B and embeds conductive regions 68 connected together and to the first face 67A through metal vias 69 for electrical connection between the MMICs 53-56. Possible vias (not shown) may connect the conductive regions 68 also to the second face 67B of the PCB 52. The first face 67A of the PCB 52 moreover carries the surface electrical connections 63 (here not visible) and the synchronization line 64.

[0047] In particular (see also FIG. 5), the synchronization line 64 is here formed by a synchronization track 66 comprising a rectilinear portion 66A and branching portions 66B extending from the rectilinear portion 66A as far as respective solder balls 65 arranged at the terminals of the MMICs 53-56 intended to receive/emit the synchronization signal LO (denoted in FIG. 5 by LOin for the input terminals and by LOout for the output terminals). For instance, the branching portions 66B connecting to the solder ball 65A coupled to the input terminal LOin and to the output terminal LOout of the Master MMIC 53 of FIG. 5 are represented by dashed lines in FIG. 6.

[0048] In practice, in the embodiment shown in FIG. 5, the rectilinear portion 66A of the synchronization line 64 extends only underneath the Master MMIC 53 and the second

[0049] Slave MIMIC 85, even though all the MMICs 53-56 have the empty row, and the branching portions 66B are connected to two solder balls 65 (solder balls 65A and 65B in FIG. 6) for the Master MIMIC 53 and to a single solder ball 65 for the MMICs 54-56.

[0050] However, the rectilinear portion 66A is not necessarily formed by a single segment that traverses the Master MIMIC 53 and the second Slave MIMIC 85, but may be formed by a broken line, only the portions thereof crossing the single MMICs 53 and 55 being preferably linear.

[0051] The synchronization track 66 may be formed in the same way as the surface electrical connections 63 formed on the first face 67A of the PCB 52, for example, as a copper track, and typically has a much lower thickness than the solder balls 65, even when these are slightly deformed after soldering, as visible in FIG. 7.

[0052] FIGS. 8-10 show an electronic device 70 implementing a different solution for routing the synchronization signal LO. Here, the MMICs comprise a microstrip (having a grounded region arranged underneath) or a coplanar waveguide (having grounded regions in the same plane as the waveguide). The microstrip or coplanar waveguide is formed above the dice, and extends practically throughout the width of each MMIC to connect opposite sides thereof. Connection with the terminals LOin and LOout is obtained through conductive tracks formed on the PCB and connected to the microstrip or coplanar waveguide through solder balls. This solution, shown in FIGS. 8 and 9 as regards bonding of the MMICs through the eWLB technique, may be used also in case of bonding of the MMICs with the FC-BGA technique, as discussed below.

[0053] In FIGS. 8 and 9, the MMICs (here designated by 83-86) have a coupling face 81, are formed as shown in FIG. 4, and each comprise a die 73 integrating electronic components (designated as a whole by 74), a peripheral region 76, and a dielectric layer 72. Metal connection lines 75, represented schematically, extend in the dielectric layer 72 and are connected with solder balls 95, as described above with reference to FIG. 4. Furthermore, also here, for clarity, the Slave MMICs 84-86 are referred to as first, second, and third Slave MMICs. It should be noted that here, albeit not shown, each die 73 derives from dicing a processed semiconductor wafer and comprises a semiconductor substrate (not shown) overlaid by one or more insulating layers (not shown) accommodating metal connection lines (not shown either), in a per se known manner.

[0054] Furthermore, as in FIG. 5, in FIG. 8, the MMICs 83-86 are arranged side-by-side, between a receiving antenna structure, RX antenna 90, and a transmitting antenna structure, TX antenna 91, and are coupled to the RX antenna 90 and TX antenna 91 through surface electrical connections 93 formed on the PCB (designated by 92) comprising, in a known way, a body 97 of dielectric material embedding conductive regions 98 connected together and to the first face 97A through metal vias 99.

[0055] Specifically, as regards the embodiment of FIGS. 8 and 9, each MMIC 83-86 has a conductive strip 71 formed in the dielectric layer 72 of the Master MIMIC 83 and of the Slave MMICs 84-86.

[0056] The conductive strips 71 are here formed using a redistribution layer RDL.

[0057] FIG. 10 shows a variant of FIG. 9, where the MMICs 83-86 are bonded using the FC-BGA technique.

[0058] Here, the electronic device, designated by 70′, has conductive strips 71′ formed in a metal layer similar to the ones used for forming metal connection lines 88, similar to the metal connection lines 18 of FIG. 3, within a connection substrate 89, similar to the connection substrate 7 of FIG. 3. In FIG. 10 the plates 8 are not shown, and the underfill layer, the bumps, and the caps are designated, respectively, by 77, 79, and 80.

[0059] In both cases of FIGS. 9 and 10, the conductive strips 71, 71′ extend approximately throughout the width of the MMICs 83-86 (and thus of the dielectric layer 72 or of the connection substrate 89), ending only at a short distance from the edge thereof.

[0060] It should be noted that, in this context, the term width of the MMICs 53-56 indicates the size in the adjacency direction of the MMICs 53-56.

[0061] As shown in FIG. 8, the electronic device 70, 70′ has a synchronization line 96 formed by the conductive strips 71, 71′ of some of the MMICs 83-86 (the ones crossed by the synchronization line 96) and track portions 94 formed on the PCB 92. The conductive strips 71, 71′ and the track portions 94 forming the synchronization line 96 are connected together by the solder balls 95.

[0062] In detail, the synchronization line 96 is here formed by the conductive strips 71, 71′ of the Master MMIC 83 and of the second Slave MMIC 85 (arranged in FIGS. 9 and 10 to the right of the Master MMIC 83). The conductive strips 71, 71′ are not electrically coupled to any of the components 74 and are connected to the respective solder balls 95 of only the Master MMIC 83 and the second Slave MMIC 85. Consequently, the conductive strips 71, 71′ of the first Slave MMIC 84 (located furthest to the left in FIG. 8 and partially visible in FIGS. 9 and 10) and of the third Slave MMIC 86 (located furthest to the right in FIG. 8 and not visible in FIGS. 9 and 10) are floating (or connected to an appropriate fixed potential, for example, ground).

[0063] As an alternative to the above, the conductive strips 71, 71′ of the first Slave MMIC 84 and of the third Slave MMIC 86 may be connected to respective solder balls 95, but these are not connected to any metal line, or are possibly connected only to a common ground line, if envisaged.

[0064] The track portions 94 formed on the PCB 92 enable connection of the synchronization line 96 to the input terminals LOin of the MMICs 83-86 and to the output terminal LOout of the Master MMIC 83. In detail, with reference to FIGS. 9 and 10, by identifying with 95A the solder ball coupled in a not shown way to the input terminal LOin of the first Slave MMIC 84 (represented dashed in FIGS. 9 and 10 in so far as it is not crossed by the section plane); by 95B the solder ball coupled to a first end (on the left in FIGS. 9 and 10) of the conductive strip 71, 71′ of the Master MMIC 83; by 95C the solder ball coupled to a second end (on the right in FIGS. 9 and 10) of the conductive strip 71, 71′ of the Master MMIC 83; and by 95D the solder ball coupled to a first end (on the left in FIGS. 9 and 10) of the conductive strip 71, 71′ of the second Slave MMIC 85, a first track portion 94A connects the solder ball 95A of the Slave MMIC 85 to the solder ball 95B of the Master MMIC 83 and to a solder ball (not visible) coupled in a way not shown to the input terminal LOin of the Master MMIC 83; a second track portion 94B connects the solder ball 95C of the Master MMIC 83 to the solder ball 95D of the second Slave MMIC 85 and to a solder ball (not visible) coupled in a way not shown to the output terminal LOout of the Master MMIC 83; a third track portion 94C (shown only in FIG. 8) connects the second end of the conductive strip 71 of the second Slave MMIC 85 to solder balls (not visible) coupled to the input terminal LOin of the second Slave MMIC 85 and to the input terminal LOin of the third Slave MMIC 86.

[0065] It should be noted that this solution can be applied also in case of a wire-bonding/solder ball mixed technique, as evident to the person skilled in the art.

[0066] FIGS. 11-13 show an electronic device 100 implementing a different solution for routing the synchronization signal LO. Here, the MMICs have a microstrip or a coplanar waveguide integrated within the die, and the microstrip or coplanar waveguide extends throughout the width of each die to connect opposite sides thereof. Connection with the terminals LOin and LOout takes place through metal connection lines or wires internal to the MMICs and conductive tracks formed on the PCB. This solution, shown in FIGS. 11 and 12 as regards bonding the MMICs 83-86 through the eWLB technique, can be used also in the case of coupling of the MMICs 83-86 with the FC-BGA technique or with the wire-bonding technique, as discussed hereinafter with reference to FIG. 13.

[0067] In detail, as shown in FIGS. 11 and 12, where same parts of the electronic device 70 of FIGS. 8 and 9 are designated by the same reference numbers and are not described any further, and the dice 73 are represented as formed by a semiconductor substrate 104 overlaid by an insulation layer 105, each MMIC 83-86 has a conductive strip 101 of metal, here formed by a metallization layer extending within the insulating layer 105 of each die 73. Each conductive strip 101 is here formed directly underneath a surface 73A of the respective die 73. In case of the Master MMIC 83 and of the second Slave MMIC 85, each conductive strip 101 is connected at its own ends to respective solder balls 95 arranged on the edges of each MMIC 83, 85, by vias and contact pads 103 formed in the insulating layer 105, and respective metal connection lines 102 formed in the dielectric layer 72 and similar to the metal connection lines 71. In case of the first and third Slave MMICs 84, 86, the conductive strips 101 are not electrically connected to the electronic components 74 of the electronic device 100, as discussed above for the conductive strips 71, 71′.

[0068] In practice, in this case, the conductive strips 101 forming the microstrips or coplanar waveguides are manufactured at wafer level, together with the components 74, and are already present when the wafer is diced to the individual dice 73.

[0069] This solution may moreover be applied both in case of bonding using the FC-BGA bonding technique (in which case, the conductive strips 101 are electrically coupled to the solder balls 95 through bumps and a bonding support as shown in FIG. 10) and to electronic devices configured to work at low frequency and provided with packages coupled to a PCB by wire bonding (wire-bonding packages).

[0070] For instance, FIG. 13 shows an electronic device 110 having the connection scheme of FIG. 11, but where the MMICs are connected through wire bonding. Consequently, same parts with the electronic device 100 of FIGS. 11 and 12 are designated by the same reference numbers and are not described any further.

[0071] In particular, in the example shown in FIG. 13, each MMIC 83-86 comprises bonding wires 115 connecting respective contact pads 103 to pins 116. Also here, the contact pads 103 are arranged at opposite ends of the conductive strips 101; each conductive strip 101 is formed within the insulation layer 105 of each die 73 and extends practically throughout the width thereof In FIG. 13, for simplicity, the insulation layer 105 is shown as a single layer covering the semiconductor substrate 104 of each die 72 and open only at the contact pads 103. However, the insulation layer 105 may be formed by different layers arranged on top of each other, in a known way.

[0072] The dice 73 and the bonding wires 115 are covered by a packaging layer 117 or a layer containing dielectric material, for example, molded resin (but the packaging layer may be formed according to any known packaging technique, as obvious to the person skilled in the art). The packaging layer 117 embeds also the pins 116 on all sides, except for the backside, where they are in direct electrical contact with the track portions 94 of the synchronization line 96.

[0073] As in FIG. 12, in FIG. 13 only the conductive strips 101 of the Master MMIC 83 and of the second Slave MIMIC 85 are connected through the bonding wires 115. Consequently, the conductive strips 101 of the first and third MMICs 84, 86 are floating (or connected to an appropriate fixed potential, for example, ground). FIG. 13 thus shows with a dashed line (in so far as arranged in a parallel plane to the section plane) the bonding wire 115 connecting the input terminal LOin of the first Slave MIMIC 84 to the first track portion 94A that is in electrical connection with an end of the conductive strip 101 of the Master MMIC 83, as explained above with reference to FIG. 11.

[0074] The MMICs and the electronic device described herein have numerous advantages.

[0075] In particular, the described solution allows the synchronization signal generated by the Master MIMIC to be carried to the Slave MMICs without requiring an additional connection level in the PCB scheme, and thus at low costs.

[0076] The described packaging structure allows the synchronization signal LO to be carried using (at least in part) the same conduction layer of the radiofrequency signals exchanged with the antenna structures 60, 61, 90, 91.

[0077] The path of the synchronization signal LO is simplified and may be minimal, thus reducing loss phenomena or layout complexity.

[0078] Finally, it is clear that modifications and variations may be made to the integrated circuit and to the electronic device described and shown herein, without thereby departing from the scope of the present disclosure. For instance, the described different embodiments may be combined so as to provide further solutions.

[0079] For example, the MMICs may be arranged also not aligned to each other, but simply arranged side-by-side between the RX and TX antenna structures. In this case, the synchronization track 70 may comprise a broken line.

[0080] The electronic device may comprise integrated circuits of a different type, even operating at different frequencies from radiofrequencies.

[0081] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.