Patent classifications
H01L2924/19032
Semiconductor package with integrated harmonic termination feature
A semiconductor package includes a metal flange having a lower surface and an upper surface opposite the lower surface. An electrically insulating window frame is disposed on the upper surface of the flange. The electrically insulating window frame forms a ring around a periphery of the metal flange so as to expose the upper surface of the metal flange in a central die attach region. A first electrically conductive lead is disposed on the electrically insulating window frame and extends away from a first side of the metal flange. A second electrically conductive lead is disposed on the electrically insulating window frame and extends away from a second side of the metal flange, the second side being opposite the first side. A first harmonic filtering feature is formed on a portion of the electrically insulating window frame and is electrically connected to the first electrically conductive lead.
SEMICONDUCTOR STRUCTURE INCLUDING PLURALITY OF CHIPS ALONG WITH AIR GAP AND MANUFACTURING METHOD THEREOF
The present disclosure provides a semiconductor structure including a first chip having a first dielectric surface, a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, and an air gap between the second dielectric surface and the first dielectric surface. The first chip includes a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines each having a sidewall partially exposed from the first dielectric surface. The present disclosure further provides a method for manufacturing the semiconductor structure described herein.
Impedance controlled electrical interconnection employing meta-materials
A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation.
Electronic device and manufacturing method of electronic device
An electronic device includes a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, a mold resin arranged on a side of the semiconductor device, an insulating layer arranged over the semiconductor device and the mold resin, a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer, a second wiring layer formed over the insulating layer and includes a first area disposed at a part overlapping with the second grounded layer and a second area disposed on a side of an end part of the second grounded layer, a via that couples the first wiring layer and the second area of the second wiring layer, and a grounded conductor formed inside the insulating layer at a position overlapping with the second area of the second wiring layer.
Gateless switch with capacitively-coupled contacts
A switch includes an input contact and an output contact to a conducting channel. At least one of the input and output contacts is capacitively coupled to the conducting channel. A control contact is located outside of a region between the input and output contacts, and can be used to adjust the switch between on and off operating states. The switch can be implemented as a radio frequency switch in a circuit.
Methods for forming microwave tunable composited thin-film dielectric layer
Methods of curing a polymer layer on a substrate using variable microwave frequency are provided herein. In some embodiments, methods of curing a polymer layer on a substrate using variable microwave frequency include (a) forming a first thin-film polymer layer on a substrate, the first thin-film polymer layer including at least one first base dielectric material and at least one microwave tunable material, (b) applying a variable frequency microwave energy to the substrate and the first thin-film polymer layer to heat the substrate and the first thin-film polymer layer to a first temperature, and (c) adjusting the variable frequency microwave energy applied to the substrate and the first thin-film polymer layer to tune at least one material property of the first thin-film polymer layer.
SEMICONDUCTOR DEVICE
A semiconductor device includes the following elements. A chip has a main surface substantially parallel with a plane defined by first and second directions intersecting with each other. A power amplifier amplifies an input signal and outputs an amplified signal from plural output terminals. First and second filter circuits attenuate harmonics of the amplified signal. The first filter circuit includes a first capacitor connected between the plural output terminals and a ground. The second filter circuit includes a second capacitor connected between the plural output terminals and a ground. On the main surface of the chip, the plural output terminals are disposed side by side in the first direction, and the first capacitor is disposed on a side in the first direction with respect to the plural output terminals, while the second capacitor is disposed on a side opposite the first direction with respect to the plural output terminals.
Electronic device including coupling structure along with waveguide, and electronic equipment
An electronic device includes a first electronic component including a first signal line and a first ground conductor surface, a second electronic component that is placed above the first electronic component and includes a second signal line and a second ground conductor surface opposed to the first ground conductor surface, a waveguide including the first ground conductor surface, the second ground conductor surface, and a pair of first ground conductor walls that are opposed to each other and are placed between the first ground conductor surface and the second ground conductor surface, a first transducing part that transduces a signal between the first signal line and the waveguide, and a second transducing part that transduces a signal between the second signal line and the waveguide.
ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE
An electronic device includes a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, a mold resin arranged on a side of the semiconductor device, an insulating layer arranged over the semiconductor device and the mold resin, a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer, a second wiring layer formed over the insulating layer and includes a first area disposed at a part overlapping with the second grounded layer and a second area disposed on a side of an end part of the second grounded layer, a via that couples the first wiring layer and the second area of the second wiring layer, and a grounded conductor formed inside the insulating layer at a position overlapping with the second area of the second wiring layer.
Semiconductor Package with Integrated Harmonic Termination Feature
A semiconductor package includes a metal flange having a lower surface and an upper surface opposite the lower surface. An electrically insulating window frame is disposed on the upper surface of the flange. The electrically insulating window frame forms a ring around a periphery of the metal flange so as to expose the upper surface of the metal flange in a central die attach region. A first electrically conductive lead is disposed on the electrically insulating window frame and extends away from a first side of the metal flange. A second electrically conductive lead is disposed on the electrically insulating window frame and extends away from a second side of the metal flange, the second side being opposite the first side. A first harmonic filtering feature is formed on a portion of the electrically insulating window frame and is electrically connected to the first electrically conductive lead.