Patent classifications
H01L2924/19033
Transition structure and high-frequency package
A transition structure disposed in a package is disclosed. The transition structure comprises a first ground lead and a second ground lead; and a signal lead, disposed between the first ground lead and the second ground lead, wherein the first ground lead and the second ground lead have an exterior edge and an interior edge, the signal lead is coupled to a metal line formed on a printed circuit board (PCB) and a signal terminal of the die within the package; wherein an exterior gap formed between the first ground lead and the second ground lead at the exterior edge is wider than an interior gap formed between the first ground lead and the second ground lead at the interior edge.
IN-PACKAGE RF WAVEGUIDES AS HIGH BANDWIDTH CHIP-TO-CHIP INTERCONNECTS AND METHODS FOR USING THE SAME
In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.
Integrated chip scale packages
Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same
In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.
SEMICONDUCTOR CHIP
The present technology relates to a semiconductor chip that can ensure a low impedance current path in an I/O ring while suppressing attenuation of radio frequency signals. The semiconductor chip includes: an I/O ring surrounding a core circuit; first and second pads serving as input/output terminals for radio frequency signals; and a radio frequency signal transmission line electrically connected to the first and second pads and the core circuit. The radio frequency signal transmission line is formed above the I/O ring. The present technology is applicable to a semiconductor chip that performs input and output of RF signals.
INTEGRATED CHIP SCALE PACKAGES
Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
Transition Structure and High-Frequency Package
A transition structure disposed in a package is disclosed. The transition structure comprises a first ground lead and a second ground lead; and a signal lead, disposed between the first ground lead and the second ground lead, wherein the first ground lead and the second ground lead have an exterior edge and an interior edge, the signal lead is coupled to a metal line formed on a printed circuit board (PCB) and a signal terminal of the die within the package; wherein an exterior gap formed between the first ground lead and the second ground lead at the exterior edge is wider than an interior gap formed between the first ground lead and the second ground lead at the interior edge.
Integrated chip scale packages
Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
INTEGRATED CHIP SCALE PACKAGES
Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
High density interconnection and wiring layers, package structures, and integration methods
An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.