A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.

An electronics package is disclosed. The electronics package includes a first radio frequency (RF) substrate layer, a second RF substrate layer, and a plurality of conductive layers disposed adjacent to at least one of the first RF substrate layer and the second RF substrate layer and including an inner conductive layer disposed between and adjacent to both the first RF substrate layer and the second RF substrate layer. The inner conductive layer bonds the first RF substrate layer to the second RF substrate layer. The electronics package also includes a plurality of conductive interconnects extending through the first RF substrate layer and the second RF substrate layer and electrically coupled between at least two of the plurality of conductive layers.

A front-end module includes: a substrate including a first connection member in which at least one first insulating layer and at least one first wiring layer are alternately stacked, a second connection member in which at least one second insulating layer and at least one second wiring layer are alternately stacked, and a core member disposed between the first and second connection members; a radio-frequency component mounted on a surface of the substrate and configured to amplify a main band of an input RF signal or filter bands outside the main band; an inductor disposed on a surface of the core member and electrically connected to the radio-frequency component; and a ground plane disposed on another surface of the core member. The core member includes a core insulating layer thicker than an insulating layer among at least one first insulating layer and the at least one second insulating layer.

A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, and a second semiconductor device. The interposer substrate is disposed over the package substrate and includes a silicon substrate. The interposer substrate has a bottom surface facing and adjacent to the package substrate, a top surface opposite the bottom surface, and a cavity formed on the top surface. The first semiconductor device is disposed on the top surface of the interposer substrate. The second semiconductor device is received in the cavity and electrically connected to the first semiconductor device and/or the interposer substrate.

A semiconductor device has a shielding layer over a semiconductor package. A plurality of slot lines define a location to form a slot in the shielding layer. The slot is formed in the shielding layer by cutting along the slot lines with a laser controlled by a scanner to read the slot lines. The slot lines include a left boundary slot line and right boundary slot line. The slot can be cut in the shielding layer by performing an edge cut along the slot lines, and performing a peel back to form the slot in the shielding layer. Alternatively, the slot can be cut in the shielding layer by performing a first cut in a first direction along the slot lines, and performing a second cut in a second direction opposite the first direction along the slot lines to form the slot in the shielding layer.

A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.

A semiconductor package includes a first package having a first side and a second side opposing the first side. The first package comprises a first electronic component and a second electronic component arranged in a side-by-side manner on the second side. A second package is mounted on the first side of the first package. The second package comprises a radiative antenna element. A connector is disposed on the second side.

The present disclosure provides a power module and a method for manufacturing the power module. The power module includes a chip, a passive element and connection pins. The connection pins are provided on a pin-out surface of the power module, and are electrically connected to at least one of a chip terminal of the chip and the passive element; a projection of the chip on the pin-out surface of the power module does not overlap with a projection of the passive element on the pin-out surface of the power module, and an angle between the terminal-out surface of the chip and the pin-out surface of the power module is greater than 45° and less than 135°.

Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.