It is an object to provide a Cu alloy bonding wire for a semiconductor device that can satisfy required performance in high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device according to the present invention, each of abundance ratios of crystal orientations <100>, <110> and <111> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis out of crystal orientations on a wire surface is 3% or more and less than 27% in average area percentage.

A method of fabricating an electronic device includes depositing a metal layer having external leads on a carrier. A photoresist material layer is patterned on the leads. A dielectric layer is formed over the metal layer such that surfaces of metal pillars from the metal layer are exposed. The photoresist material layer is removed from the leads, and the dielectric layer and the metal layer are removed from the carrier. A die is attached to the first surface of the dielectric layer. The die includes contacts on a surface of the die that contacts the dielectric layer such that the contacts are aligned with and connect to the exposed surfaces of the metal pillars. A mold compound is formed over the die, the dielectric layer, the metal traces, and the metal pillars of the metal layer, but not over the leads of the metal layer.

It is an object to provide a Cu alloy bonding wire for a semiconductor device that can satisfy required performance in high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device according to the present invention, each of abundance ratios of crystal orientations <100>, <110> and <111> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis out of crystal orientations on a wire surface is 3% or more and less than 27% in average area percentage.

A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.

A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.

A tableted epoxy resin composition for encapsulation of semiconductor devices and a semiconductor device encapsulated using the tableted epoxy resin composition, the tableted epoxy resin composition satisfying the following conditions (i) a proportion of tablets of the tableted epoxy resin composition having a diameter of greater than or equal to 0.1 mm and less than 2.8 mm and a height of greater than or equal to 0.1 mm and less than 2.8 mm is about 97 wt % or more, as measured by sieve analysis using ASTM standard sieves; (ii) the tablets have a packed density of greater than about 1.7 g/mL; and (iii) a ratio of packed density to cured density of the tablets is about 0.6 to about 0.87.

A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.

Quality control testing for a batch of electronic modules. A series of tests are performed on manufactured electronic modules, including tests sensitive to the failure rate of previously tested modules. Specifically, a first test comprised of two phases is performed on the module batch. Further screening is then performed responsive to detection of a wire sweep failure in a subset of failed modules from the first test phase. The further screening is on modules that passed the first test phase and excludes modules that failed the first test phase.

A semiconductor element, a substrate on which the semiconductor element is mounted, a connecting portion formed constituted by an arrangement of a plurality of wirings, a casing in which the substrate is disposed on a side of a bottom surface thereof and the semiconductor element and the connecting portion are accommodated therein, and an insulating sealing material filled in the casing, are provided. The plurality of wirings constituting the connecting portion are aligned in a loop shape in a same direction, and each height thereof is arranged such that each of the wiring has a height which is gradually increased one after another toward one direction in the arrangement.

An electronic package is provided, in which an electronic element is arranged on a carrier structure having a plurality of wire-bonding pads arranged on a surface of the carrier structure, and a plurality of bonding wires are connected to a plurality of electrode pads of the electronic element and the plurality of wire-bonding pads. Further, among any three adjacent ones of the plurality of wire-bonding pads, a long-distanced first wire-bonding pad, a middle-distanced second wire-bonding pad and a short-distanced third wire-bonding pad are defined according to their distances from the electronic element. Therefore, even if the bonding wires on the first to third wire-bonding pads are impacted by an adhesive where a wire sweep phenomenon occurred when the flowing adhesive of a packaging layer covers the electronic element and the bonding wires, the bonding wires still would not contact each other, thereby avoiding short circuit problems.