A quantum cascade laser device includes a QCL element and a package. A light-emitting window through which laser light emitted from the QCL element passes is provided on a side wall of the package. The light-emitting window includes a small-diameter hole, a large-diameter hole larger than the small-diameter hole, a counterbore surface having an annular shape that connects the small-diameter hole and the large-diameter hole, and a window member disposed inside the large-diameter hole. An incident surface of a window member includes a first region in which an anti-reflection film is provided, and a second region metallized and formed in an annular shape to be separated from the first region and to surround the first region. The second region is joined to the counterbore surface through a solder member.

An optical emitting device includes a base, a thermoelectric cooler, an optical communication assembly and a circuit board. The base includes a main body and a stem connected with each other. The stem extends from a basal surface of the main body, and a normal of a supporting surface of the stem is non-parallel to a normal of the basal surface of the main body. The thermoelectric cooler is disposed on the supporting surface of the stem. The optical communication assembly is disposed on the thermoelectric cooler, and the thermoelectric cooler is between the optical communication assembly and the stem. The circuit board is disposed on the base and passes through the main body and electrically connected with the optical communication assembly.

An external cavity diode laser has been developed to achieve a linear frequency chirp over a broad bandwidth using a silicon photonic filter chip as the external cavity. By appropriately chirping the cavity phase using the gain chip and/or a cavity phase modulator on the silicon photonic chip along with simultaneously varying the filter resonance, approximately linear frequency chirping can be accomplished for at least 50 GHz, although desirable structures with useful lesser chirp bandwidths are also described. With careful control of the chip design, it is possible to achieve predictable behavior of mode jumps along with large scannable ranges within a mode, which allows for stitching together segments of linear chirp through a mode jump to provide for very large chirp bandwidths greater than 1 THz.

An optical modulator carrier assembly includes a optical modulator, a transmission line substrate, a first via, a second via and a wire having an inductor component provided on a second surface of the transmission line substrate, and electrically connecting between the another end of the first via and the another end of the second via. The one end of the first via, the cathode electrode pad, the terminating resistor, the one end of the second via are arranged on the in this order.

An optical sub-assembly includes a diode submount structure, a diode mounted to the diode submount, and a thermoelectric cooler (TEC). The TEC is in thermal contact with the diode, and the diode is positioned between the diode submount structure and the TEC.

Provided are a subminiature optical transmission module and a method for manufacturing same. The optical transmission module includes: a mold body having a first surface and a second surface opposite to each other; multiple edge-type light emitting elements, each of which is molded inside the mold body by fitting same to the first surface so as to match with the first surface and generates an optical signal in the edge direction of a chip; and an optical component disposed on one side thereof so as to optically multiplex multiple optical signals incident from the multiple edge-type light emitting elements and to output same, wherein the identical height is configured between the surface of each light emitting element and the optical axis of the optical component, and the edge direction of the chip is parallel to the first surface of the mold body.

A socket for an electronic component includes: an electrically insulating material; a base body including at least one opening configured for accommodating an electrically conductive pin configured for being electrically connected to the electronic component, the at least one opening being sealed with the electrically insulating material such that the electrically conductive pin is fed through the at least one opening while being electrically insulated from the base body; and a shell part including a pedestal configured for accommodating the electronic component, at least the shell part of the socket including a metal with a thermal conductivity of at least 100 W/mK.

In part, in one aspect, the disclosure relates to a system including a photonic integrated circuit (PIC) assembly, comprising a PIC comprising: a first bond pad disposed inward from an edge of the PIC a first distance; and a first wire having a first length, the first wire electrically connected to the first bond pad and extending therefrom, wherein the first distance is greater than 0.4 mm.

Provided is a back side emitting light source array device and an electronic apparatus, the back side emitting light source array device includes a substrate, a distributed Bragg reflector (DBR) provided on a first surface of the substrate, a plurality of gain layers which are provided on the DBR, the plurality of gain layers being spaced apart from one another, and each of the plurality of gain layers being configured to individually generate light, and a nanostructure reflector provided on the plurality of gain layers opposite to the DBR, and including a plurality of nanostructures having a sub-wavelength shape dimension, wherein a reflectivity of the DBR is less than a reflectivity of the nanostructure reflector such that the light generated is emitted through the substrate.

A method for on-silicon integration of a III-V-based material component includes providing a first substrate having a silicon-based optical layer including a waveguide, transferring a second substrate of III-V-based material on the optical layer, and forming the III-V component from the second substrate, so as to enable a coupling between the waveguide and the III-V component, by preserving a III-V-based material layer extending laterally. The method also includes forming by epitaxy from the III-V layer, an InP:Fe-based structure laterally bordering the III-V component, forming a layer including contacts configured to contact the III-V component, and transferring a third silicon-based substrate onto the layer including the contacts.