A buried typed semiconductor optical device includes a semiconductor substrate having a pair of grooves extending in a first direction. An upper surface of a buried layer has a first region that is adjacent to a mesa stripe structure, overlaps with a corresponding one of the pair of grooves, is inclined so as to be higher in a second direction from the mesa stripe structure, and on which a passivation film is not formed. The upper surface of the buried layer has a second region that does not overlap with any of the pair of grooves, is flat, and is higher than a lower end of the first region, and on which the passivation film is formed. The upper surface of the buried layer has a connection region between the first region and the second region at a same height as the second region.

A buried typed semiconductor optical device includes a semiconductor substrate having a pair of grooves extending in a first direction. An upper surface of a buried layer has a first region that is adjacent to a mesa stripe structure, overlaps with a corresponding one of the pair of grooves, is inclined so as to be higher in a second direction from the mesa stripe structure, and on which a passivation film is not formed. The upper surface of the buried layer has a second region that does not overlap with any of the pair of grooves, is flat, and is higher than a lower end of the first region, and on which the passivation film is formed. The upper surface of the buried layer has a connection region between the first region and the second region at a same height as the second region.

A photonic integrated circuit including a photonic device and a gain element, said gain element formed by a process including: depositing by epitaxy a first doped layer onto a substrate; depositing by epitaxy an active layer capable of optical gain onto the first doped layer; depositing by epitaxy a second doped layer onto the active layer; pattern etching at least the second doped layer and the active layer to form a first ridge; and depositing by epitaxy a current blocking layer laterally adjacent to the first ridge at least partially filling the volume of active layer that was removed by the pattern etching; wherein the current blocking layer forms a portion of the photonic device.

A photonic integrated circuit including a photonic device and a gain element, said gain element formed by a process including: depositing by epitaxy a first doped layer onto a substrate; depositing by epitaxy an active layer capable of optical gain onto the first doped layer; depositing by epitaxy a second doped layer onto the active layer; pattern etching at least the second doped layer and the active layer to form a first ridge; and depositing by epitaxy a current blocking layer laterally adjacent to the first ridge at least partially filling the volume of active layer that was removed by the pattern etching; wherein the current blocking layer forms a portion of the photonic device.

In the arrayed semiconductor optical device, a plurality of semiconductor optical devices including a first semiconductor optical device and a second semiconductor optical device are monolithically integrated on a semiconductor substrate, each of the semiconductor optical devices includes a first semiconductor layer having a multiple quantum well layer and a grating layer disposed on an upper side of the first semiconductor layer, a layer thickness of the first semiconductor layer of the first semiconductor optical device is thinner than a layer thickness of the first semiconductor layer of the second semiconductor optical device, and a height of the grating layer of the first semiconductor optical device is lower than a height of the grating layer of the second semiconductor optical device corresponding to difference in the layer thickness of the first semiconductor layer.

In the arrayed semiconductor optical device, a plurality of semiconductor optical devices including a first semiconductor optical device and a second semiconductor optical device are monolithically integrated on a semiconductor substrate, each of the semiconductor optical devices includes a first semiconductor layer having a multiple quantum well layer and a grating layer disposed on an upper side of the first semiconductor layer, a layer thickness of the first semiconductor layer of the first semiconductor optical device is thinner than a layer thickness of the first semiconductor layer of the second semiconductor optical device, and a height of the grating layer of the first semiconductor optical device is lower than a height of the grating layer of the second semiconductor optical device corresponding to difference in the layer thickness of the first semiconductor layer.

A quantum cascade laser includes: a laser structure including first and second end faces, a semiconductor mesa, and a supporting base; and a first electrode on the semiconductor mesa. The first and second end faces are arranged in a direction of a first axis. The semiconductor mesa has first and second mesa portions which are disposed between the first and second end faces. The semiconductor mesa has a first mesa width at a boundary between the first and second mesa portions, and a second mesa width smaller than the first mesa width at an end of the second mesa portion, and has a width varying from the first mesa width in a direction from the boundary to the second end face. The second mesa portion includes a high specific-resistance region having a specific-resistance higher than that of a conductive semiconductor region included in the first and second mesa portions.

For epitaxial-side-down bonding of quantum cascade lasers (QCLs), it is important to optimize the heat transfer between the QCL chip and the heat sink to which the chip is mounted. This is achieved by using a heatsink with high thermal conductivity and by minimizing the thermal resistance between the laser active region and said heatsink. In the epi-down configuration concerned, the active region of the QCL is located only a few micrometers away from the heatsink, which is preferable from a thermal standpoint. However, this design is challenging to implement and often results in a low fabrication yield if no special precautions are taken. Since the active region is very close to the heatsink, solder material may ooze out on the sides of the chip during the bonding process and may short-circuits the device, rendering it unusable. To avoid this happening, the invention proposes to provide a trench all around the chip with the exception of the two waveguide facets, i.e. the ends of the active region. This trench may be etched into the otherwise standard QCL chip or otherwise machined into the chip, providing an initially empty space for the volume of solder displaced by the chip during the epi-down bonding process, which empty space is occupied by the surplus solder without contacting the side of the chip and thus short-circuiting the device.

To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (AWG) comprised of InP is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5 to 1.0 in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type InP is formed over the AWG with a V/III ratio of 2000 or more. Thereby, it is possible to obtain excellent multiple quantum wells (MQWs) by reducing a film thickness variation of the AWG. Moreover, the cover layer having side faces where a (0-11) plane almost perpendicular to a substrate surface mainly appears can be formed. A sectional shape of a lamination part of the cover layer and the AWG becomes an approximately rectangular shape. Therefore, an electrification region can be enlarged and it is possible to reduce a resistance of the semiconductor device.

A quantum cascade laser includes a laser structure including a substrate and a semiconductor laminate region, the substrate having a principal surface that includes first to third areas that extend in a direction of a first axis, the substrate having first and second end faces arranged in the direction of the first axis, the semiconductor laminate region having first and second mesas and a semiconductor mesa which are arranged on the first to third areas, respectively; and a first semiconductor film disposed on the third area, side faces of the first and second mesas, and an end face of the semiconductor mesa. The laser structure includes a first region including the semiconductor mesa, and a second region including the first and second mesas. The second region includes a recess defined by the third area, the side face of the first mesa, and the side face of the second mesa.