Patent classifications
H01S5/2272
Semiconductor laser diode and method of fabricating the same
Provided are a semiconductor laser diode and a method for fabricating the same. The semiconductor laser diode includes a c-plane substrate, a group III nitride layer disposed on the c-plane substrate, and a first semiconductor layer, an active layer, and a second semiconductor layer disposed on the group III nitride layer in the stated order, wherein each of the first semiconductor layer and the second semiconductor layer is exposed to the outside of the semiconductor laser diode.
ARRAYED SEMICONDUCTOR DEVICE, OPTICAL TRANSMISSION MODULE, OPTICAL MODULE, AND METHOD FOR MANUFACTURING THEREOF
In the arrayed semiconductor optical device, a plurality of semiconductor optical devices including a first semiconductor optical device and a second semiconductor optical device are monolithically integrated on a semiconductor substrate, each of the semiconductor optical devices includes a first semiconductor layer having a multiple quantum well layer and a grating layer disposed on an upper side of the first semiconductor layer, a layer thickness of the first semiconductor layer of the first semiconductor optical device is thinner than a layer thickness of the first semiconductor layer of the second semiconductor optical device, and a height of the grating layer of the first semiconductor optical device is lower than a height of the grating layer of the second semiconductor optical device corresponding to difference in the layer thickness of the first semiconductor layer.
Semiconductor laser and manufacturing method thereof
In a semiconductor laser, a block layer is provided on both sides of a mesa-type semiconductor part having an n-type cladding layer, an active layer, and a p-type cladding layer. The block layer has: a p-type block layer formed on the side surface of the mesa-type semiconductor part and over a p-type semiconductor substrate; a high-resistance layer formed over the p-type block layer; and an n-type block layer formed over the high-resistance layer, which has a higher resistance than that of the p-type block layer. By providing the high-resistance layer between the p-type block layer and the n-type block layer, the thickness of the p-type block layer can be controlled and a leakage current (flow of a hole) can be reduced. Further, the distance between the n-type cladding layer and the n-type block layer can be secured, and hence a leakage current (flow of an electron) can be prevented.
Apparatus and method for tuning a laser source emission wavelength employing a laser source contact comprising electrode segments
A laser source or a plurality of laser sources in a photonic integrated circuit (PIC) are provided with an electrical contact that is either segmented or is connected to a series of vernier resistor segments for supply of current to operate the laser source. In either case, at least one segment of the laser contact or at least one vernier resistor segment can be trimmed in order to vary the amount of current supplied to the laser source resulting in a change to its current density and, thus, a change in its operational wavelength while maintaining the current supplied to the laser source constant.
Process of forming semiconductor optical device and semiconductor optical device
A semiconductor laser diode type of a buried-hetero structure (BH-LD) is disclosed. The LD provides a mesa, a first burying layer, and a second burying layer, where the burying layers are provided in respective sides of the mesa so as to expose a top of the mesa. The mesa includes a lower cladding layer, an active layer, and an upper cladding layer, where the cladding layers have conduction type opposite to each other and, combined with the burying layers, constitute a carrier confinement structure. The second burying layer has an even surface overlapping with an even surface of the first burying layer, and has a thickness in a portion of the even surface that is thinner than a thickness thereof in a portion except for the even surface.
Semiconductor optical device
A semiconductor optical device includes an active layer, the active layer including a plurality of quantum well layers having gain peak wavelengths different from one another in a layering direction thereof, and a plurality of barrier layers, wherein the quantum well layers and the barrier layers are alternately layered over each other, and an n-type dopant has been added in the plurality of quantum well layers having gain peak wavelengths different from one another and in the plurality of barrier layers.
Quantum cascade laser array
A quantum cascade laser includes a substrate having first and second substrate regions arranged along a first axis; a laser structure body including a laser body region having laser waveguide structures extending along the first axis, the laser structure body including first and second regions respectively including the first and second substrate regions, the laser body region having an end facet located at a boundary between the first and second regions, the second region including a terrace extending along the first axis from a bottom edge of the end facet; a plurality of first electrodes disposed on the laser waveguide structures; a plurality of pad electrodes disposed on the terrace; and a plurality of wiring metal bodies each of which includes a first portion on the terrace and a second portion on the end facet. The pad electrodes are connected with the first electrodes through the wiring metal bodies, respectively.
Method for fabricating semiconductor device
A method for fabricating a semiconductor device on a semiconductor substrate, wherein the semiconductor device is adapted to provide target lasing properties, the method includes creating, a mask layer over the semiconductor substrate, the mask layer having at least one opening to expose a region of the semiconductor substrate, etching using a first etching process the exposed region, utilizing inductively coupled plasma with preselected first set of parameters to obtain a baseline mesa profile, the baseline mesa profile having a baseline mesa angle, re-etching using a second etching process the etched region, utilizing inductively coupled plasma with preselected second set of parameters, to alter the baseline mesa profile to obtain a requisite mesa profile having a requisite mesa angle defined by the target lasing properties and the requisite mesa angle being different from the baseline mesa angle, removing the mask layer and defining a p-n junction for the semiconductor substrate.
MANUFACTURABLE GALLIUM AND NITROGEN CONTAINING COUPLED WAVEGUIDE DEVICES
The present disclosure provides optical devices and methods for forming the optical devices. In some embodiments, the optical devices include active and passive regions. The active regions may include gallium and nitrogen containing epitaxial material, and the passive regions may include waveguide structures. The active and passive regions may be arranged on a carrier wafer in an end-to-end configuration. In other embodiments, the optical devices include laser devices or gain regions and dielectric waveguides. The laser devices or gain regions may include gallium and nitrogen containing epitaxial material.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (AWG) comprised of InP is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5 to 1.0 in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type InP is formed over the AWG with a V/III ratio of 2000 or more. Thereby, it is possible to obtain excellent multiple quantum wells (MQWs) by reducing a film thickness variation of the AWG. Moreover, the cover layer having side faces where a (0-11) plane almost perpendicular to a substrate surface mainly appears can be formed. A sectional shape of a lamination part of the cover layer and the AWG becomes an approximately rectangular shape. Therefore, an electrification region can be enlarged and it is possible to reduce a resistance of the semiconductor device.