Patent classifications
H02M7/483
Multi-level medium voltage data center static synchronous compensator (DCSTATCOM) for active and reactive power control of data centers connected with grid energy storage and smart green distributed energy sources
Systems and methods for supplying power (both active and reactive) at a medium voltage from a DCSTATCOM to an IT load without using a transformer are disclosed. The DCSTATCOM includes an energy storage device, a two-stage DC-DC converter, and a multi-level inverter, each of which are electrically coupled to a common negative bus. The DC-DC converter may include two stages in a bidirectional configuration. One stage of the DC-DC converter uses a flying capacitor topology. The voltages across the capacitors of the flying capacitor topology are balanced and switching losses are minimized by fixed duty cycle operation. The DC-DC converter generates a high DC voltage from a low or high voltage energy storage device such as batteries and/or ultra-capacitors. The multi-level, neutral point, diode-clamped inverter converts the high DC voltage into a medium AC voltage using a space vector pulse width modulation (SVPWM) technique.
Multi-level medium voltage data center static synchronous compensator (DCSTATCOM) for active and reactive power control of data centers connected with grid energy storage and smart green distributed energy sources
Systems and methods for supplying power (both active and reactive) at a medium voltage from a DCSTATCOM to an IT load without using a transformer are disclosed. The DCSTATCOM includes an energy storage device, a two-stage DC-DC converter, and a multi-level inverter, each of which are electrically coupled to a common negative bus. The DC-DC converter may include two stages in a bidirectional configuration. One stage of the DC-DC converter uses a flying capacitor topology. The voltages across the capacitors of the flying capacitor topology are balanced and switching losses are minimized by fixed duty cycle operation. The DC-DC converter generates a high DC voltage from a low or high voltage energy storage device such as batteries and/or ultra-capacitors. The multi-level, neutral point, diode-clamped inverter converts the high DC voltage into a medium AC voltage using a space vector pulse width modulation (SVPWM) technique.
THREE-LEVEL INVERTER, CONTROL METHOD, AND SYSTEM
A three-level inverter includes controllable switch components T1 to T6. Each of the controllable switch components includes a parallel connected junction capacitor and an anti-parallel connected diode. A first terminal of T1 is connected to a positive direct current bus, a second terminal of T4 is connected to a negative direct current bus, a second terminal of T1 is connected to first terminals of T2 and T5. A controller is configured to: in a positive half cycle, control T3 to be conducted after T1 is conducted, and control T3 to be disconnected before T1 is conducted next time; and in a negative half cycle, control T2 to be conducted after T4 is conducted, and control T2 to be disconnected before T4 is conducted next time. The three-level inverter can balance voltages of the controllable switch components.
THREE-LEVEL INVERTER, CONTROL METHOD, AND SYSTEM
A three-level inverter includes controllable switch components T1 to T6. Each of the controllable switch components includes a parallel connected junction capacitor and an anti-parallel connected diode. A first terminal of T1 is connected to a positive direct current bus, a second terminal of T4 is connected to a negative direct current bus, a second terminal of T1 is connected to first terminals of T2 and T5. A controller is configured to: in a positive half cycle, control T3 to be conducted after T1 is conducted, and control T3 to be disconnected before T1 is conducted next time; and in a negative half cycle, control T2 to be conducted after T4 is conducted, and control T2 to be disconnected before T4 is conducted next time. The three-level inverter can balance voltages of the controllable switch components.
POWER CONVERTER
A power converter includes a PCB having opposing first and second sides, and a plurality of first commutation units and first capacitor unit disposed on the PCB. Each first commutation unit includes a first discrete component and a second discrete component. The second end of the first discrete component is electrically coupled to the first end of the second discrete component, and the first capacitor unit is electrically coupled to the first ends of the first discrete components and the second ends of the second discrete components in the plurality of first commutation units, respectively. The first discrete components and the second discrete components in the plurality of first commutation units are arranged in a row. The first discrete component and the second discrete component in each first commutation unit form a commutation loop together with the first capacitor unit.
MULTI-LEVEL INVERTING BUCK-BOOST CONVERTER ARCHITECTURE
A multi-level converter comprises one or more flying capacitors configured to operate at balanced voltages. The multi-level converter comprises a plurality of switching groups comprising pairs of switches operable to transfer energy to and from an inductor and the one or more flying capacitors for inverting an input voltage to an inverted output voltage. The multi-level converter comprises the inductor configured to operate according to an inductor frequency greater than a switching frequency used to control the plurality of switching groups.
Current feedback control for a power converter with multiple feedback loops
A method performed by a control system of a power electronics converter. A first part of a grid-side current controller runs a first feedback control algorithm having a first control cycle time and includes at least proportional control using a proportional gain. A third part of the controller runs a third feedback control algorithm having the first control cycle time and acting on an output from the first control algorithm after SOA limits have been applied and includes counteracting the proportional control of the first feedback control algorithm. A second part of the controller runs a second feedback control algorithm having a second control cycle time, less than the first control cycle time, and acting on an output from the third control algorithm with the same polarity as the first control algorithm and includes proportional control using the proportional gain.
Converter arrangement
A converter apparatus includes a string of electrically interconnected modules that includes a first group of modules comprising a first module and a second group of modules comprising a second module. A first screen is connected to a first defined electric potential and is located adjacent the first group of modules and a second screen is connected to a second defined electric potential and is located adjacent the second group of modules. During operation of the converter apparatus a resonance loop is created from the first module via the first and second screens and the second module back to the first module. A damping unit is located in the resonance loop and is set to dampen electromagnetic noise.
POWER CONVERSION SYSTEMS AND METHODS
According to at least one aspect of the disclosure, a bi-directional AC/DC converter is provided comprising a DC-power connection configured to be coupled to a DC-power source, an AC-power connection configured to be coupled to at least one of an AC-power source or a load, a multiplexer having a plurality of multiplexer switches, at least one interleaved bridge circuit having a plurality of bridge switches coupled to the multiplexer, and a positive DC node and a negative DC node coupled to the plurality of multiplexer switches, wherein the plurality of bridge switches includes at least two bridge switches coupled between the AC-power connection and at least one of the positive DC node or the negative DC node.
SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND POWER CONVERSION APPARATUS
An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.