A series multiplex inverter includes a power conversion unit, a phase difference selection unit, a drive signal generation unit, and a drive signal output unit. The phase difference selection unit selects, from among a plurality of phase difference candidates, the phase difference between rectangular wave voltages from a plurality of single-phase inverters. The drive signal generation unit generates a plurality of drive signals that causes the different single-phase inverters to output a plurality of rectangular wave voltages sequentially out of phase by the phase difference selected by the phase difference selection unit. The drive signal output unit outputs the plurality of drive signals generated by the drive signal generation unit to the plurality of single-phase inverters.

An apparatus utilizing additive interleaved switchmode (PWM) power conversion stages, having minimal or no output filter, to achieve high bandwidth or even ideally instantaneous power conversion. The additive process may involve voltage stacking of isolated PWM converters, which are interleaved in time, or may involve a single input power supply and inductively combining output currents of PWM power converters interleaved in time, with either additive circuit having minimal or no output filtering. This circuit may overcome limitations for the frequency of feedback control loops once thought to be physical limitations, such as, fundamental switching frequency, output filter delay and the Nyquist criteria.

An apparatus utilizing additive interleaved switchmode (PWM) power conversion stages, having minimal or no output filter, to achieve high bandwidth or even ideally instantaneous power conversion. The additive process may involve voltage stacking of isolated PWM converters, which are interleaved in time, or may involve a single input power supply and inductively combining output currents of PWM power converters interleaved in time, with either additive circuit having minimal or no output filtering. This circuit may overcome limitations for the frequency of feedback control loops once thought to be physical limitations, such as, fundamental switching frequency, output filter delay and the Nyquist criteria.

A new class of DC-AC inverter consists of a buck or two buck converters and two or four low frequency switches, and it achieves ultra-high efficiency, reactive power flow capability, small size and low cost in grid-connected applications.

An apparatus utilizing additive interleaved switchmode (PWM) power conversion stages, having minimal or no output filter, to achieve high bandwidth or even ideally instantaneous power conversion. The additive process may involve voltage stacking of isolated PWM converters, which are interleaved in time, or may involve a single input power supply and inductively combining output currents of PWM power converters interleaved in time, with either additive circuit having minimal or no output filtering. This circuit may overcome limitations for the frequency of feedback control loops once thought to be physical limitations, such as, fundamental switching frequency, output filter delay and the Nyquist criteria.

An apparatus utilizing additive interleaved switchmode (PWM) power conversion stages, having minimal or no output filter, to achieve high bandwidth or even ideally instantaneous power conversion. The additive process may involve voltage stacking of isolated PWM converters, which are interleaved in time, or may involve a single input power supply and inductively combining output currents of PWM power converters interleaved in time, with either additive circuit having minimal or no output filtering. This circuit may overcome limitations for the frequency of feedback control loops once thought to be physical limitations, such as, fundamental switching frequency, output filter delay and the Nyquist criteria.

An apparatus utilizing additive interleaved switchmode (PWM) power conversion stages, having minimal or no output filter, to achieve high bandwidth or even ideally instantaneous power conversion. The additive process may involve voltage stacking of isolated PWM converters, which are interleaved in time, or may involve a single input power supply and inductively combining output currents of PWM power converters interleaved in time, with either additive circuit having minimal or no output filtering. This circuit may overcome limitations for the frequency of feedback control loops once thought to be physical limitations, such as, fundamental switching frequency, output filter delay and the Nyquist criteria.

An apparatus utilizing additive interleaved switchmode (PWM) power conversion stages, having minimal or no output filter, to achieve high bandwidth or even ideally instantaneous power conversion. The additive process may involve voltage stacking of isolated PWM converters, which are interleaved in time, or may involve a single input power supply and inductively combining output currents of PWM power converters interleaved in time, with either additive circuit having minimal or no output filtering. This circuit may overcome limitations for the frequency of feedback control loops once thought to be physical limitations, such as, fundamental switching frequency, output filter delay and the Nyquist criteria.

A power conversion device includes a plurality of converter cells 1, and the converter cell 1 includes: an upper arm 13u, which includes a semiconductor switching element 11u configured to allow conduction in only one direction and a diode 12u connected in anti-parallel to the semiconductor switching element 11u; and a lower arm 13b, which is connected to the upper arm 13u, and includes a semiconductor switching element 11b configured to allow reverse conduction and a diode 12b connected in anti-parallel to the semiconductor switching element lib, in which the semiconductor switching element 11b and the diode 12b of the lower arm 13b are simultaneously set to conductive states to split an electric current to flow through the diode 12b to the semiconductor switching element 11b.

A power conversion device includes a plurality of converter cells 1, and the converter cell 1 includes: an upper arm 13u, which includes a semiconductor switching element 11u configured to allow conduction in only one direction and a diode 12u connected in anti-parallel to the semiconductor switching element 11u; and a lower arm 13b, which is connected to the upper arm 13u, and includes a semiconductor switching element 11b configured to allow reverse conduction and a diode 12b connected in anti-parallel to the semiconductor switching element lib, in which the semiconductor switching element 11b and the diode 12b of the lower arm 13b are simultaneously set to conductive states to split an electric current to flow through the diode 12b to the semiconductor switching element 11b.