A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.

An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.

A wireless station includes at least one oscillator to output a reference signal, and an error calculator to calculate a frequency of the reference signal and calculate a frequency error by subtracting a target frequency of the reference signal from the calculated frequency of the reference signal. The wireless station further includes a modulation data generator to generate modulation data by adding a correction value, varying in negative correlation with the frequency error calculated by the error calculator, to data to be transmitted, and a modulator to conduct frequency modulation on the basis of the modulation data and the data to be transmitted.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus includes a plurality of unit variable reactance structures including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.

A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.

An example of a device for generating a broadband frequency signal comprises a first controlled oscillator, a second controlled oscillator, a phase-locked loop for feeding back an output signal of a controlled oscillator to the corresponding controlled oscillator, and a mixer. The mixer is configured to generate the broadband frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator. The device may, for example, be realized by means of a single phase-locked loop. A further example relates to a device for generating a frequency signal with a controlled oscillator and a phase-locked loop with a further controlled oscillator and a mixer in the feedback path of the phase-locked loop. Examples further relate to a high-frequency device for emitting a high-frequency signal and a method for generating a broadband frequency signal.

A frequency synthesizer circuit included in a sensor circuit of a computer system may include a voltage-controlled oscillator circuit that may generate an oscillator signal. A three-point injection technique may be used to modulate the frequency of the oscillator signal. The three-point injection includes a low-frequency component that drives a feedback divider, and two high-frequency components that drive the voltage-controlled oscillator circuit. The strengths of the three injection points are aligned using samples of a tune signal generated using results of a comparison of a referenced signal and a frequency divided version of the oscillator signal.