In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive an otw signal that is associated with low-path pass information and transmission data. The apparatus may apply a cost function and an update function to the otw signal prior to sending the otw signal to an oscillator. The apparatus may determine a correction factor for use in estimating a gain of the oscillator based at least in part on an output of the update function.

Embodiments are directed to apparatuses and methods involving a phase-error tracking circuit. An example apparatus includes a divide-by phase locked loop (PLL) circuit to generate a continuous wave signal that sweeps over a frequency range in response to a divider feedback signal and to a reference signal. The apparatus further includes the phase-error tracking circuit defining a phase-error window in which the divide-by PLL circuit is to lock based on a slope associated with a rate of change of the frequency range, and indicating whether a phase error between the divider feedback signal and the reference signal coincides with the phase-error window.

An example of a device for generating a broadband frequency signal comprises a first controlled oscillator, a second controlled oscillator, a phase-locked loop for feeding back an output signal of a controlled oscillator to the corresponding controlled oscillator, and a mixer. The mixer is configured to generate the broadband frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator. The device may, for example, be realized by means of a single phase-locked loop. A further example relates to a device for generating a frequency signal with a controlled oscillator and a phase-locked loop with a further controlled oscillator and a mixer in the feedback path of the phase-locked loop. Examples further relate to a high-frequency device for emitting a high-frequency signal and a method for generating a broadband frequency signal.

This disclosure relates to fractional-N phase-locked loops. A digital filter can filter out quantization noise from a modulator. Separate paths can process an integer part associated with an output signal of the digital filter and a fractional part associated with the output signal of the digital filter. The separate paths can be combined in the fractional-N phase-locked loop, for example, as a weighted sum.

A synthesizer comprises a two-point modulation phase locked tow, TPM PLL, circuit configured to receive a frequency tuning signal and to generate a stepped chirp signal in an intermediate frequency range by applying a two-point modulation PLL on the frequency tuning signal, and a subsampling PLL circuit configured to receive the stepped chirp signal in a mm-wave frequency range and to generate a smoothened chirp signal in a mm-wave frequency range by applying a subsampling PLL on the stepped chirp signal.

A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive an otw signal that is associated with low-path pass information and transmission data. The apparatus may apply a cost function and an update function to the otw signal prior to sending the otw signal to an oscillator. The apparatus may determine a correction factor for use in estimating a gain of the oscillator based at least in part on an output of the update function.

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Aspects of this disclosure relate to transmitting and/or receiving a frequency-shift keying signal including a packet that includes a preamble and a payload. The preamble has a first modulation index that has a smaller magnitude than a second modulation index of the payload. This can enhance frequency correction in a receive device that receives the packet.

A synthesizer comprises a first two-point modulation phase locked loop, TPM PLL, circuit that receives a first reference clock signal at a first reference frequency and a feedback signal at a feedback frequency and generates a first chirp signal by applying a two-point modulation PLL on the first reference clock signal, a second integer-n TPM PLL circuit that receives a second reference clock signal at a second reference frequency lower than the first reference frequency and generates a second chirp signal by applying a TPM PLL on the second reference clock signal, a mixer that downconverts the first chirp signal by the second chirp signal to obtain the feedback signal at the feedback frequency corresponding to the difference of the frequency of the first chirp signal and the second chirp signal, and a feedback path that feeds back the feedback signal to the first TPM PLL circuit.