An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

A synthesizer comprises a first two-point modulation phase locked loop, TPM PLL, circuit that receives a first reference clock signal at a first reference frequency and a feedback signal at a feedback frequency and generates a first chirp signal by applying a two-point modulation PLL on the first reference clock signal, a second integer-n TPM PLL circuit that receives a second reference clock signal at a second reference frequency lower than the first reference frequency and generates a second chirp signal by applying a TPM PLL on the second reference clock signal, a mixer that downconverts the first chirp signal by the second chirp signal to obtain the feedback signal at the feedback frequency corresponding to the difference of the frequency of the first chirp signal and the second chirp signal, and a feedback path that feeds back the feedback signal to the first TPM PLL circuit.

A synthesizer comprises a two-point modulation phase locked tow, TPM PLL, circuit configured to receive a frequency tuning signal and to generate a stepped chirp signal in an intermediate frequency range by applying a two-point modulation PLL on the frequency tuning signal, and a subsampling PLL circuit configured to receive the stepped chirp signal in a mm-wave frequency range and to generate a smoothened chirp signal in a mm-wave frequency range by applying a subsampling PLL on the stepped chirp signal.

A wireless communication device includes a receiver circuit, a phase shift control circuit, and a digital phase-locked loop (DPLL) circuit. The receiver circuit includes a down-converter circuit that is used to apply down-conversion to an input signal according to a local oscillator (LO) signal. The phase shift control circuit is used to generate a phase shift signal. The DPLL circuit is used to generate the LO signal locked to an initial frequency under a frequency-lock state. In response to the phase shift signal, the DPLL circuit is further used to make the LO signal have a different frequency without leaving the frequency-lock state.

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

A clock generator including a phase frequency detector configured to compare a phase and a frequency of a reference clock signal with a phase and a frequency of a first output clock signal and generate a detection signal based on a difference in the phases and frequencies of the clock signals; a loop filter configured to generate a first control voltage signal based on the detection signal; a first voltage controlled oscillator configured to generate and output a first output clock signal based on the first control voltage signal, a modulation filter configured to generate a modulation voltage signal based on the reference clock signal and generate a second control voltage signal by combining the modulation voltage signal and the first control voltage signal, and a second voltage controlled oscillator configured to generate and output a second output clock signal based on the second control voltage signal is provided.

This disclosure relates to an apparatus, system, and method for generating uplink transmissions using a polar architecture including a phase locked loop with potential for two point injection. According to some embodiments, frequency resources allocated for a transmission may be determined. A cartesian baseband signal may be generated for the uplink transmission. The cartesian baseband signal may be converted to a polar baseband signal, including a baseband phase signal and an amplitude signal. Modulation parameters, potentially including whether to use one point injection or two point injection with a phase locked loop, may be determined. The baseband phase signal may be upconverted to an RF phase signal according to the determined modulation parameters. The RF phase signal may be amplified according to the amplitude signal to produce an RF signal. The RF signal may be transmitted.

A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired frequency modulated continuous wave; a digitally controlled oscillator (DCO) configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter (TDC), wherein the feedback loop is configured to feed back the DCO output signal; a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto. The TDC receives a representation of the DCO output signal and a reference frequency signal to sample the DCO output signal and outputs multiple selectable delays of the DCO output signal. A digital synthesizer circuit sensor is configured to sense an operational condition of the digital synthesizer circuit and select one of the multiple selectable delays output from the TDC in response to the sensed operational condition. A re-timer circuit is coupled to the digital synthesizer circuit sensor and configured to synchronize the selected delayed DCO output signal with the reference frequency signal.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.