A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.

An audio FM transmitter is disclosed that may achieve high-precision frequency control as well as compact size and low cost by enabling FM modulation using a fractional-N type PLL circuit.

An apparatus for PLL bandwidth expansion including a compensation filter and a phase locked loop, where the compensation filter is programmed with a compensation function derived based on programmable coefficients and parameters of a transmitting device, a frequency response of the phase locked loop, and a wanted frequency response.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a multiplexed selection signal, the first clock output signal having a second duty cycle; and adjust the second duty cycle responsive to at least a set of control signals or a phase difference between a first and second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to generate a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to adjust a second duty cycle of a first clock output signal responsive to a set of control signals or a phase difference between a first phase clock signal and a second phase clock signal of the first set of phase clock signals. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.