An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

A multistage amplifier includes: N amplifiers (N≥2), a (k+1).sup.th amplifier cascaded to a k.sup.th amplifier (1≤k≤N−1), and each amplifier being configured to amplify a multicarrier signal; and an extraction circuit including an input and an output, the input being connected to an output of a j.sup.th amplifier (1≤j≤N−1), and the output providing a compensation signal to an input of a (j+1).sup.th amplifier or an output of the (j+1).sup.th amplifier. The extraction circuit includes a filter circuit connected to the output of the j.sup.th amplifier that extracts a distortion frequency component of n times a differential frequency f2−f1 (n≥1), a phase shifter cascaded to the filter circuit that shifts a phase of the component, and a gain adjustment circuit cascaded to the phase shifter that adjusts an amplitude of the component and generates the compensation signal.

A power amplifier may comprise: an element for amplifying an electrical signal received through an input terminal, and outputting the amplified electrical signal through an output terminal; a first impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a fundamental component at the input terminal; a second impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a multiplied harmonic component at the input terminal; a third impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the fundamental component at the output terminal; a fourth impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the multiplied harmonic component at the output terminal; a first frequency separation circuit which prevents an impedance change by the first impedance adjustment circuit with respect to the frequency of the multiplied harmonic component at the input terminal, and prevents an impedance change by the second impedance adjustment circuit with respect to the frequency of the fundamental component at the input terminal; and a second frequency separation circuit which prevents an impedance change by the third impedance adjustment circuit with respect to the frequency of the multiplied harmonic component at the output terminal, and prevents an impedance change by the fourth impedance adjustment circuit with respect to the frequency of the fundamental component at the output terminal.

A system for split-frequency amplification, preferably including: one or more primary-band amplification stages, one or more secondary-band amplification stages, one or more band-splitting filters, and/or one or more signal couplers. An analog canceller including one or more split-frequency amplifiers. A mixer including one or more split-frequency amplifiers. A voltage-controlled oscillator including one or more split-frequency amplifiers. A method for split-frequency amplification, preferably including: receiving an input signal, separating the input signal into signal portions, and/or amplifying the signal portions, and optionally including combining the amplified signal portions and/or providing one or more output signals.

A power amplifier system having a power amplifier with a signal input and a signal output and bias circuitry is disclosed. The bias circuitry includes a bandgap reference circuit coupled between a reference node and a fixed voltage node. A bias generator has a bias input coupled to the reference node and a bias output coupled to the signal input. Also included is a first digital-to-analog converter having a first converter output coupled to the reference node, a first voltage input, and a first digital input, wherein the first digital-to-analog converter is configured to adjust a reference voltage at the reference node in response to a first digital setting received at the first digital input. The first digital setting correlates with an indication of temperature of the power amplifier.

An RF amplifier for implementation in SiGe HBT technology is described. The RF amplifier has a cascode stage comprising a common base (CB) transistor and a common emitter (CE) transistor arranged in series between a first voltage rail and a second voltage rail. An RF input is coupled to the base of the CE transistor and an RF output is coupled to the collector of the CB transistor. The RF amplifier includes a CB power-down circuit arranged between the base of the CB transistor and the second voltage rail and a CE power-down circuit arranged between the base of the CE transistor and the second voltage rail. In a power-down mode the CE power-down circuit couples the base of the common-emitter-transistor to the second voltage rail. The CB power-down mode circuit couples the base of the CB transistor to the second voltage rail via a high-ohmic path.

A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.

Power amplification system is disclosed. A power amplification system can include a Class-E push-pull amplifier including a transformer balun. The power amplification can further include a reactance compensation circuit coupled to the transformer balun. In some embodiments, the reactance compensation circuit is configured to reduce variation over frequency of a fundamental load impedance of the power amplification system.

A power amplifier circuit includes a first transistor, wherein a radio frequency signal is inputted to a base or gate of the first transistor; a second transistor having an emitter connected to a collector or drain of the first transistor, wherein a first voltage is supplied to a collector of the second transistor, and a first amplified signal obtained by amplifying the radio frequency signal is outputted from the collector of the second transistor; and a third transistor configured to supply a bias voltage to a base of the second transistor. A second voltage is supplied to a collector or drain of the third transistor, a third voltage corresponding to the first voltage is supplied to a base or gate of the third transistor, and the bias voltage, which corresponds to the third voltage, is supplied from an emitter or source of the third transistor.

A digital power amplifier comprising two or more individually activatable amplifiers. The outputs of the amplifiers are connected causing an activated amplifier of the two or more amplifiers to load modulate another activated amplifier of the two or more amplifiers.