Circuitry includes a first RF power amplifier, a second RF power amplifier, a third RF power amplifier, a first bias signal generator, and a second bias signal generator. The first RF power amplifier and the second RF power amplifier are each configured to amplify RF signals for transmission in a first carrier network. The third RF power amplifier is configured to amplify RF signals for transmission in a second carrier network. In a first mode, the first bias signal generator provides a bias signal to the first RF power amplifier and the second bias signal generator provides a bias signal to the second RF power amplifier. In a second mode, the first bias signal generator and the second bias signal generator each provide a portion of a bias signal to the third RF power amplifier.

A power amplifier of the present invention comprises a first cascode including a MOSFET and a JFET and a first capacitor electrically connected between the source and the drain of the JFET. Two such power amplifiers in parallel form a differential power amplifier. In the differential amplifier a second capacitor can be electrically connected between the source and the drain of the second JFET. Another differential power amplifier comprises a first capacitor electrically connected between the gate of the first MOSFET and the source of the second MOSFET, and a second capacitor electrically connected between the gate of the second MOSFET and the source of the first MOSFET. Some of these differential power amplifiers also include capacitors electrically connected between the sources and the drains of the JFETs.

Provided herein are apparatus and methods for power enhancement of self-biased distributed amplifiers with gate bias networks. By sampling output power a gate bias network with a filter network can adjust gate bias so as to improve the P1 dB compression point and the Psat saturation power level of a self-biased distributed amplifier. Advantageously the filter network can be derived using passive components thereby making it an easy to implement and cost effective approach to improve linearity and output power.

A power amplifier of the present invention comprises a first cascode including a MOSFET and a JFET and a first capacitor electrically connected between the source and the drain of the JFET. Two such power amplifiers in parallel form a differential power amplifier. In the differential amplifier a second capacitor can be electrically connected between the source and the drain of the second JFET. Another differential power amplifier comprises a first capacitor electrically connected between the gate of the first MOSFET and the source of the second MOSFET, and a second capacitor electrically connected between the gate of the second MOSFET and the source of the first MOSFET. Some of these differential power amplifiers also include capacitors electrically connected between the sources and the drains of the JFETs.

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

A power amplifier of the present invention comprises a first cascode including a MOSFET and a JFET and a first capacitor electrically connected between the source and the drain of the JFET. Two such power amplifiers in parallel form a differential power amplifier. In the differential amplifier a second capacitor can be electrically connected between the source and the drain of the second JFET. Another differential power amplifier comprises a first capacitor electrically connected between the gate of the first MOSFET and the source of the second MOSFET, and a second capacitor electrically connected between the gate of the second MOSFET and the source of the first MOSFET. Some of these differential power amplifiers also include capacitors electrically connected between the sources and the drains of the JFETs.

A compound semiconductor device includes: a compound semiconductor region having a surface in which a step is formed; a first electrode formed so as to overlie the upper surface of the step, the upper surface being a non-polar face; and a second electrode formed along a side surface of the step so as to be spaced apart from the first electrode in a vertical direction, the side surface being a polar face.

A Radio Frequency (RF) amplifier includes a depletion mode semiconductor device having a gate, a bias device and an inverting circuit. The depletion mode semiconductor device may be a HEMT and/or a MESFET. The bias device is configured to generate a bias voltage. The inverting circuit is configured to generate an inverted bias voltage from the bias voltage, and to apply the inverted bias voltage to the gate. Related circuits and methods are described.

Polyphase filter circuitry including: an input node to receive an input signal V.sub.IN having a dominant frequency f.sub.PPF; and a common-source amplifier circuit. The common-source amplifier circuit includes a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor C.sub.PFF connected to its source terminal; and for the common-source amplifier circuit, the output resistance R.sub.M1 at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PFF are define the frequency response of the common-source amplifier circuit so that, based on the input signal V.sub.IN, a signal V.sub.LEAD is generated at the drain terminal of the transistor M1 which leads the input signal V.sub.IN in phase by a given phase shift .sub.LEAD and a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG.

A Radio Frequency (RF) amplifier includes a depletion mode semiconductor device having a gate, a bias device and an inverting circuit. The depletion mode semiconductor device may be a HEMT and/or a MESFET. The bias device is configured to generate a bias voltage. The inverting circuit is configured to generate an inverted bias voltage from the bias voltage, and to apply the inverted bias voltage to the gate. Related circuits and methods are described.