A power control system for audio power amplifiers, especially in the automotive segment, dynamically controlling the output voltage through the reading of the input and output currents, and other parameters, automatically adjusting the amplifier to the load and to the operation conditions, allowing that the amplifier always operates within the safe operation range.

This application relates to method and apparatus for driving acoustic transducers, such as speakers or haptic transducers. A transducer driver circuit (200) has a hysteretic comparator (201) configured to compare, with hysteresis, an input signal (S.sub.IN) received at a first comparator input to a feedback signal (S.sub.FB) received at a second comparator input. Based on the comparison the hysteretic comparator (201) generates a pulse-width modulation (PWM) signal (S.sub.PWM) at a comparator output (206). An inductor (203) is coupled between the comparator output and an output node (204). In use a resistive component (208), which may comprise the transducer (301) is coupled to output node (204). The inductor (203) and resistive component (208) provide filtering to the PWM signal (S.sub.PWM). A feedback path extends between the output node (204) and the second comparator input to provide the feedback signal (S.sub.FB).

A wideband envelope modulator comprises a direct current (DC)-to-DC switching converter connected in series with a linear amplitude modulator (LAM). The DC-DC switching converter includes a pulse-width modulator that generates a PWM signal with modulated pulse widths representing a time varying magnitude of an input envelope signal or a pulse-density modulator that generates a PDM signal with a modulated pulse density representing the time varying magnitude of the input envelope signal, a field-effect transistor (FET) driver stage that generates a differential PWM or PDM drive signal, a high-power output switching stage that is driven by the PWM or PDM drive signal, and an output energy storage network including a low-pass filter (LPF) of order greater than two that filters a switching voltage produced at an output switching node of the high-power output switching stage.

A Class D amplifier module includes a semiconductor chip and n inductors. The semiconductor chip includes n output stages, n high-side drivers, and n low-side drivers. The semiconductor chip and the n inductors are housed in a single package and operate according to a control signal received from an external processor.

A power supply modulator includes: a first switching element in which a first voltage is applied to the first terminal and the second terminal is connected to an output terminal; a second switching element in which the third terminal is connected to the output terminal and the second terminal, and a second voltage is applied to the fourth terminal; a first driver circuit in which the first voltage is applied to the fifth terminal and the sixth terminal is grounded, to control opening and closing of the first switching element by a change in a resistance value between the fifth and sixth terminals; and a second driver circuit in which the seventh terminal is grounded and the second voltage is applied to the eighth terminal, to control opening and closing of the second switching element by a change in a resistance value between the seventh and eighth terminals.

A semiconductor device includes: an operational amplifier; an external terminal configured to be attached to an external capacitor; and a resistor configured to be connected between a node, to which an output terminal and an inverting input terminal of the operational amplifier are connected in common, and the external terminal.

Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

This application describes time-encoding modulator circuitry (200), and in particular a PWM modulator suitable for use for a class-D amplifier. A forward signal path receives a digital input signal (Din) and outputs an output PWM signal (Sout) and includes a first PWM modulator (101). A feedback path provides feedback to an input of the first PWM modulator (101). The feedback path includes an ADC (203) which receive a first PWM signal (Sa) derived from the output PWM signal. The ADC (203) includes a second PWM modulator (401) which generates a second PWM signal (Sb) based on the first PWM signal. A controller (201) controls the second PWM modulator such that a PWM carrier of the second PWM signal is phase and frequency matched to a PWM carrier of the output PWM signal.

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

A power supply includes a first DC-DC converter coupled to receive power from a first power source, a second DC-DC converter coupled to receive power from a second power source, and a control block. The first DC-DC converter is operable to generate a regulated power supply voltage on an output node of the power supply. The first power source has a maximum output current limit. The second DC-DC converter is also operable to generate a regulated power supply voltage on the output node. The control block is designed to generate the regulated power supply voltage based on both of the first DC-DC converter and the second DC-DC converter.