A multi-level class D audio power amplifier for supplying an N-level drive signal to a loudspeaker. The multi-level class D audio power amplifier includes a switching matrix having controllable semiconductor switches where the switching matrix include at least (N−2) switch inputs, coupled to respective ones of (N−2) DC input voltage nodes, and at least 2*(N−2) switch outputs coupled to respective ones of 2*(N−2) intermediate nodes of a first output driver. A control circuit is configured to sequentially connect each of the (N−2) DC input voltages to a predetermined set of nodes of the 2*(N−2) intermediate nodes of the first output driver via the switching matrix in accordance with one or more of the 2*(N−1) modulated control signals of the first output driver. N is a positive integer larger than or equal to 3.

An audio signal modulation and amplification circuit includes a common-mode electric potential controller, a carrier generator, and channel circuits. The common-mode electric potential controller is configured to generate one or more first common-mode electric potentials and second common-mode electric potentials. The carrier generator is adapted to receive the first common-mode electric potential to generate a carrier signal. Each of the channel circuits includes a filter, a comparison circuit, and a driving circuit. The filter is adapted to filter an input signal and generate a filtered signal based on a corresponding one of the second common-mode electric potentials. The comparison circuit is configured to compare the potential of the carrier signal with the potential of the filtered signal to generate a pulse-width modulation signal. The driving circuit is configured to be turned on or off in response to the pulse-width modulation signal to output a load driving signal.

A semiconductor IC includes a first radio-frequency element (e.g., an inductor in a low-noise amplifier), a second radio-frequency element (e.g., an inductor in a low-noise amplifier), a first via conductor (e.g., a via conductor that is placed between the first radio-frequency element and the second radio-frequency element and that is connected to a ground potential.

A multi-bit digital signal that is generated by modulating a baseband signal by a modulation circuit and includes components in a radio frequency band is amplified by switch-mode amplifiers (100-1, 100-2) on a bit-by-bit basis, amplified signals are band-limited by frequency-variable variable band limiting units (201-1, 201-2) and thereafter subjected to voltage-to-current conversion by voltage/current source conversion units (202-1, 202-2) provided with variable capacitances, the signals converted to current are synthesized at a synthesis point X, and a resultant signal is impedance-corrected by an impedance correction unit (203) and output as a transmission signal to an antenna of a load (300). Consequently, the present invention provides a transmitter capable of synthesizing output signals from a plurality of switch-mode amplifiers and transmitting a resultant signal while maintaining an impedance characteristic with respect to a plurality of transmit frequencies without increasing a circuit size.

An amplification circuit includes a first switching circuit that includes input terminals and first and second output terminals and that puts the second output terminal into an open state with respect to the input terminals while selectively putting the first output terminal into a state of being connected to any of the input terminals or selectively puts the second output terminal into a state of being connected to any of input terminals while putting the first output terminal into a state of being open with respect to the input terminals; a matching network that is connected to the first output terminal; an amplifier that is connected to an output side of the matching network; a second switching circuit that is connected to an output side of the amplifier; and a bypass path that electrically connects the second output terminal and an output terminal of the second switching circuit. The amplifier is a variable-gain amplifier.

An amplifier circuit for a parametric transducer, comprising: a signal processor for processing an input signal into first and second signals; and at least a pair of output stages arranged to respectively receive the first and second signals for generating amplified first and second signals respectively, which are provided to operate the parametric transducer. The input, first and second signals are arranged with a substantially similar frequency to cause a switching frequency of the amplifier circuit to be matched to a carrier frequency of the parametric transducer. A related audio device is also disclosed.

A power encoder includes a pulse width modulator for modulating a signal according to a set of thresholds to produce a pulse width modulated (PWM) signal and a switch mode power amplifier for amplifying the PWM signal by switching states of switching devices according to amplitudes of the PWM signal. At least one or combination of a distribution of values of the voltage thresholds in the set and a distribution of values of a current generated by different switching devices are non-uniform. The set of voltage thresholds includes at least two positive voltage thresholds.

A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.

The present invention relates to an amplifying device and to an amplifying system comprising the same. According to the present invention, an amplifier line-up is presented comprising four amplifying units which is operable in a Doherty mode and an outphasing mode. By integration of Chireix compensating elements in the matching networks used in the amplifying units a bandwidth improvement can be obtained.

A multi-path subsystem may include a first processing path, a second processing path, a mixed signal return path, and a calibration engine configured to: estimate and cancel a direct current (DC) offset of the mixed signal return path, estimate and cancel a DC offset between the first processing path and the second processing path, estimate and cancel a phase difference between the first processing path and a sum of the second processing path and the mixed signal return path, estimate and cancel a return path gain of the mixed signal return path, and track and correct for a gain difference between the first processing path and the second processing path.