An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.

The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.

A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.

The method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The method includes intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The system includes a power amplification device capable of minimizing the effect of envelope impedance. The power amplification device may be incorporated in a terminal and a base station.

A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.

An apparatus is disclosed including a wireless transceiver implementing transformer reconfigurability. In an example aspect, the apparatus includes a common single-ended node, a common differential node pair, and a transceiver path set. The transceiver path set includes a first transceiver path and a second transceiver path. The first transceiver path comprises a first single-ended interface and a first differential interface and includes a first transformer. The second transceiver path comprises a second single-ended interface and a second differential interface and includes a second transformer. The apparatus also includes single-ended switch circuitry and differential switch circuitry. The single-ended switch circuitry is coupled between each transceiver path of the transceiver path set and the common single-ended node. The differential switch circuitry is coupled between each transceiver path of the transceiver path set and the common differential node pair. Alternatively, an apparatus can include multiple single-ended nodes including first and second single-ended nodes.

A power amplifier module that includes a power amplifier and a controller is presented herein. The power amplifier module may include a set of transistor stages and a plurality of bias circuits. At least one transistor stage from the set of transistor stages may be in electrical communication with a first bias circuit and a second bias circuit from the plurality of bias circuits. The first bias circuit can be configured to apply a first bias voltage to the at least one transistor stage and the second bias circuit can be configured to apply a second bias voltage to the at least one transistor stage. The controller may be configured to activate one of the first bias circuit and the second bias circuit.

A radio-frequency module includes: a transmission power amplifier that includes first and second amplification transistors that are cascade connected to each other; and a mounting substrate that has first and second main surface that face each other, the transmission power amplifier being mounted on the first main surface. The first amplification transistor is arranged in a final stage and has a first emitter terminal. The second amplification transistor is arranged in a stage preceding the first amplification transistor and has a second emitter terminal. The mounting substrate has first to fourth ground electrode layers in order of proximity to the first main surface. The first emitter terminal and the second emitter terminal are not electrically connected to each other via an electrode on the first main surface and are not electrically connected to each other via the first ground electrode layer.

The method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The method includes intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The system includes a power amplification device capable of minimizing the effect of envelope impedance. The power amplification device may be incorporated in a terminal and a base station.

Embodiments of the disclosure generally relate to a method and device for improving the efficiency of a power amplifier. The apparatus comprising: a harmonic generator, configured to generate one or more harmonic according to an output signal of a power amplifier; a harmonic feedback device, configured to inject the harmonic generated by the harmonic generator to an input terminal of the power amplifier; and a harmonic eliminator, configured to eliminate the harmonic in the output signal of the power amplifier. According to embodiments of the disclosure, the efficiency of power amplifier can be improved without degrading the linearity.