A power amplification system comprises a pre-processor including a wavefront multiplexer, a set of power amplifiers, and a post-processor including a wavefront demultiplexer. The wavefront multiplexer receives concurrently N input signals, N being an integer greater than 2, performs a wavefront multiplexing transform on the N input signals by attaching N wavefronts to the N input signals respectively, and generates N first output signals. The N wavefronts are unique and mutually orthogonal. The wavefront multiplexing transform has an inverse. The N power amplifiers amplify the N first output signals and generate N amplified signals. The wavefront demultiplexer performs the inverse of the wavefront multiplexing transform on the N amplified signals and generates N second output signals, the N second output signals corresponding respectively to the N input signals. Each of the N second output signals is an amplified version of a corresponding one of the N input signals.

A circuit module includes a power amplifier, a switch, and a bypass capacitor. The power amplifier has a signal input node coupled to an input signal, a signal output node to generate an output signal, and a power input node coupled to a supply output signal of a supply modulator. The switch is coupled between the power input node of the power amplifier and the bypass capacitor. The bypass capacitor is an equivalently removable bypass capacitor coupled between the switch and a ground level.

A power supply to power amplifier (PA) distribution network may include a first power supply. The PA distribution network may further include at least one power amplifier. The power amplifier may be coupled to the first power supply. The power amplifier may include a driver stage and a power stage. The power amplifier may be coupled to the first power supply via a first switch.

A multi-level, multi-branch outphasing amplifier (20-1) includes a first branch group circuit (22-1) including a first branch circuit (11) receiving a first RF input signal (S.sub.1(t)) and first control information (S.sub.11.sub._Ctrl=V.sub.DD) and a second branch circuit (12) receiving the first input signal and second control information (S.sub.12.sub._Ctrl). Each of the first (11) and second (12) branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit (12) remains on. A second branch group circuit (22-2) includes a third branch circuit (21) receiving a second RF input signal (S.sub.2(t)) and third control information (S.sub.21.sub._Ctrl=V.sub.DD) and a fourth branch circuit (22) receiving the second input signal (S.sub.2(t)) and fourth control information (S.sub.22.sub._Ctrl). Each of the third and fourth branch circuits includes a power amplifier. The fourth control information enables the fourth branch circuit to be switched on or off while the third branch circuit remains on. A combiner (24) combines output signals of the power amplifiers to produce an output signal (S.sub.OUT(t)).

A dual-mode envelope tracking (ET) power management circuit is provided. An ET amplifier(s) in the dual-mode ET power management circuit is capable of supporting normal-power user equipment (NPUE) mode and high-power user equipment (HPUE) mode. In the NPUE mode, the ET amplifier(s) amplifies a radio frequency (RF) signal(s) to an NPUE voltage based on a supply voltage for transmission in an NPUE output power. In the HPUE mode, the ET amplifier(s) amplifies the RF signal(s) to an HPUE voltage higher than the NPUE voltage based on a boosted supply voltage higher than the supply voltage for transmission in an HPUE output power higher than the NPUE output power. The ET amplifier(s) maintains a constant load line between the NPUE mode and the HPUE mode. By maintaining the constant load line, it is possible to maintain efficiency of the ET amplifier(s) in both the NPUE mode and the HPUE mode.

A broadband linear processing system includes a pre-processing module and a set of M linear processors coupled to the pre-processing module, M being an integer greater than 1. The pre-processing module includes a wavefront multiplexer having M input ports and M output ports. The wavefront multiplexer receives M input signals at the M input ports, performs a wavefront multiplexing transform on the M input signals and outputs M narrowband signal streams at the M output ports. The wavefront multiplexing transform has an inverse. Each of the M linear processors receives and processes a corresponding one of the M narrowband signal streams, and outputs a corresponding one of M processed narrowband signal streams.

A power amplifier circuit, including: an input node configured to receive a radio frequency (RF) signal; an output node configured to output an amplified RF signal; a main path switchably coupled between the input node and the output node, and including a first plurality of amplification stages to generate a first amplified RF signal; a bypass path switchably coupled between the input node and the output node, and including at least one second amplification stage to generate a second amplified RF signal; and a coupling switch configured to reuse at least a portion of the bypass path to drive the main path to generate a third amplified RF signal.

A broadband linear processing system includes a pre-processing module and a set of M linear processors coupled to the pre-processing module, M being an integer greater than 1. The pre-processing module includes a wavefront multiplexer having M input ports and M output ports. The wavefront multiplexer receives M input signals at the M input ports, performs a wavefront multiplexing transform on the M input signals and outputs M narrowband signal streams at the M output ports. The wavefront multiplexing transform has an inverse. Each of the M linear processors receives and processes a corresponding one of the M narrowband signal streams, and outputs a corresponding one of M processed narrowband signal streams.

A broadband digital beam forming system comprises a set of Q pre-processing modules, Q being an integer greater than or equal to 2, and a set of M digital beam forming modules in communication with the Q preprocessing modules. Each of the Q preprocessing modules receives a respective one of Q broadband input signal streams and outputs M narrowband signal streams, M being an integer greater than or equal to 2. The total number of narrowband signal streams outputted by the Q pre-processing modules is Q times M. Each of the M digital beam forming modules receives corresponding Q narrowband signal streams of the Q times M narrowband signal streams, and outputs R beam signals, R being an integer greater than or equal to 1. The system further comprises a set of R post-processing modules in communication with the M digital beam forming modules. Each of the R post-processing modules receives M beam signals, each of the M beam signals being a corresponding one of the R beam signals from each of the M digital beam forming modules, and outputs a corresponding broadband output signal.

A power amplifier circuit, including: an input node configured to receive a radio frequency (RF) signal; an output node configured to output an amplified RF signal; a main path switchably coupled between the input node and the output node, and including a first plurality of amplification stages to generate a first amplified RF signal; a bypass path switchably coupled between the input node and the output node, and including at least one second amplification stage to generate a second amplified RF signal; and a coupling switch configured to reuse at least a portion of the bypass path to drive the main path to generate a third amplified RF signal.