An apparatus and methods for timing mismatch in a power amplifier includes a segmented PA with two-path timing mismatch calibration to improve ACLR performance over different signal transitions, process, voltage and temperature (PVT) variations and device aging; a fast and efficient algorithm for measuring and calibrating the delay of two paths (signal path and control path); a signal magnitude variation detection circuit, such as flash ADC, with improved comparator's performance for RF signal processing and minimum delay. A method for choosing the threshold voltage of the magnitude variation detection circuit, according to status of the signals and orthogonal frequency-division multiplexing (OFDM) related standards; other critical blocks.

A Doherty amplifier includes a carrier amplifier, a peaking amplifier, and a phase compensation circuit. The carrier amplifier 11 includes a main amplifying element and a parasitic element, and the peaking amplifier includes an auxiliary amplifying element and a parasitic element. The phase compensation circuit has a negative electrical length that allows a total electrical length of a signal transmission path starting from an output source of the main amplifying element to a power combiner to become 180N90 where N is a positive integer. In addition, a signal transmission path starting from an output source of the auxiliary amplifying element to the power combiner has an electrical length of 180M180 where M is a positive integer.

Embodiments of a method and device are disclosed. In an embodiment, a Doherty amplifier module includes a substrate including a mounting surface, and a carrier amplifier die, a first peaking amplifier die, and a second peaking amplifier die on the mounting surface. The carrier amplifier die includes a first output bond pad that has a first length and a first width. The first peaking amplifier die includes a second output bond pad including a first main pad portion having a second length and a second width and including a first side pad portion having a third length and a third width. At least one of the second width or the third width is greater than the first width. The second peaking amplifier includes a third output bond pad. A first wirebond array is coupled between the third output bond pad and at least the first side pad portion.

The disclosure provides an amplifying apparatus including a plurality of amplifying circuits and an adjusting circuit. The input terminals of the amplifying circuits are coupled to a first common node. The output terminals of the amplifying circuits are coupled to a second common node. The adjusting circuit adjusts an input signal to generate an adjusted signal to the first common node; the adjusting circuit adjusts the signal of the second common node; or the adjusting circuit adjusts the input signal to generate the adjusted signal to the first common node and adjusts the signal of the second common node. The first control signal and the second control signal respectively control the amplifying circuits and the adjusting circuit to determine the gain, the linear power, and the output current of the amplifying apparatus.

Embodiments of the present invention provide a power amplifier, a radio remote unit RRU, and a base station. A multiphase pulse width modulator performs modulation to generate N multiphase pulse-width modulation PWM signals. The multiphase pulse-width modulation PWMn signal may be amplified. The multiphase pulse-width modulation PWMn signal may be filtered and a combination may be performed at a drain or a collector of a power amplifier transistor. According to the new radio frequency amplifier in accordance with the disclosure, envelope feeding loop inductance can be effectively reduced, so that video bandwidth is increased and DPD correction performance is improved.

A transmission unit includes a first transistor that amplifies power of a first signal and outputs a second signal, a power supply circuit that supplies to the first transistor a power supply voltage that changes in accordance with an amplitude level of the first signal, and an attenuator that attenuates the first signal in such a manner that an amount of attenuation of the first signal increases with a decrease in the power supply voltage when the power supply voltage is less than a first level.

A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.

A matching network is a matching network of a power amplifier circuit that outputs a signal obtained by a differential amplifier amplifying power of a high-frequency signal. The matching network includes an input-side winding connected between differential outputs of the differential amplifier; an output-side winding that is coupled to the input-side winding via an electromagnetic field and whose one end is connected to a reference potential; a first LC series resonant circuit including a capacitive element and an inductive element connected in series with each other, and being connected in parallel with the input-side winding; and a second LC series resonant circuit including a capacitive element and an inductive element connected in series with each other, and being connected in parallel with the output-side winding.

A power amplifier circuit includes a first transistor amplifying a first signal; a second transistor amplifying a second signal; a bias circuit supplying a bias current or voltage to a base or gate of the second transistor; and an attenuator attenuating the first or second signal in accordance with a control voltage supplied from the bias circuit. The attenuator includes a first diode to which the control voltage is supplied, a third transistor including a collector connected to a supply path of the first or second signal, an emitter connected to a ground, and a base to which the control voltage is supplied from the first diode, and a capacitor connected in parallel with the first diode. The control voltage decreases as a second signal power level increases. The third transistor allows part of the first or second signal to pass to the emitter in accordance with the control voltage.

An amplification system includes a first amplification module, a second amplification module, a third amplification module I, a fourth amplification module I, a first load, a third amplification module II, a fourth amplification module II and a second load. An output terminal of the first amplification module is connected to an input terminal of the second amplification module; output terminals of the second amplification module are connected to an input terminal of the third amplification module I and an input terminal of the third amplification module II. An output terminal of the third amplification module I is connected to an input terminal of the first load through the fourth amplification module I. An output terminal of the third amplification module II is connected to an input terminal of the second load through the fourth amplification module II.