An RF module includes a switch IC having connection electrodes on a first main face and connection electrodes on a second main face; a mounting substrate which has a first mounting face at the first main face side and a second mounting face at the second main face side and in which the switch IC is mounted; signal lines for a band A, which are formed at the first mounting face side of the mounting substrate; signal lines for a band B, which are formed at the second mounting face side of the mounting substrate; a band A filter; and a band B filter. Among the band A filter and the band B filter, only the band A filter is mounted on the first mounting face and only the band B filter is mounted on the second mounting face.

A DC-to-DC converter block with multiple supply voltages includes a power circuit, the power circuit including N depletion-mode HEMT transistors (T3_1, T3_2, T3_N), N being a natural number greater than or equal to 3. The DC-to-DC converter block also includes a gate drive circuit for the N depletion-mode HEMT transistors (T3_1, T3_2, T3_N) of the power circuit, the drive circuit including depletion-mode HEMT transistors (T1_1, T2_1, T1_2, T2_2, T1_N, T2_N) configured to drive the gates of the N depletion-mode HEMT transistors (T3_1, T3_2, T3_N) of the power circuit, and the power circuit being powered by N positive and non-zero supply voltages, namely a lower supply voltage (VDD_1), an upper supply voltage (VDD_N), and (N2) intermediate supply voltages (VDD_2) distributed between the lower (VDD_1) and upper (VDD_N) supply voltages.

Disclosed are methods for biasing amplifiers and for manufacturing bias circuits bias for biasing amplifiers. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2Vbe) of the amplifying transistor.

A signal generator is configured to generate a signal with an amplitude sweep, the signal generator having circuitry comprising: a set of control components, each control component of the set being arranged to be switchably activated in parallel in the circuitry such that an amplitude of the signal has an intrinsic dependence on the number of the control components activated; a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling activation of a respective control component of the set of control components such that the control components are arranged to be activated or de-activated in a pre-determined order by shifting activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

A variable load power amplifier that improves the performance of a power amplifier that provides both envelope tracking (ET) and average power tracking (APT). The variable load power amplifier can include a plurality of amplifiers that are each selectively connectable into one of a plurality of parallel combinations, each of the plurality of parallel combinations characterized by a corresponding load line. The variable load power amplifier can also include a plurality of control elements arranged to selectively connect one or more of the plurality of amplifiers into one of the plurality of parallel combinations, each of the plurality of control elements having a respective input terminal provided to receive a respective control signal, each of the plurality of control elements responsive to the respective control signal.

Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

A high frequency module includes a first amplifier circuit, a second amplifier circuit, a first matching circuit connected to the first amplifier circuit, and a second matching circuit connected to the second amplifier circuit, wherein the first matching circuit and the second matching circuit are arranged adjacent to each another. The first matching circuit may be provided on an output side of the first amplifier circuit.

Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.

Front-end for processing 2G signal using 3G/4G paths. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

A bias circuit for power amplifiers is disclosed. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2Vbe) of the amplifying transistor.