Variable-phase amplifier circuits and devices. In some embodiments, an amplifier can include a variable-gain stage having a plurality of switchable amplification branches, with each being capable of being activated, such that a combination of one or more activated amplification branches provides respective gain level and phase shift. The plurality of switchable amplification branches can be configured such that the phase shift provided by each combination of one or more activated amplification branches compensates for a phase shift associated with the amplifier operating with the respective gain level of the variable-gain stage.

A receiving circuit and method for increasing bandwidth are provided. The receiving circuit includes a linear equalizer circuit and a variable gain amplifier. The linear equalizer circuit includes a first negative impedance converter, to generate a first capacitance. The variable gain amplifier is coupled to the linear equalizer circuit. The variable gain amplifier includes a first-stage gain circuit and a feedback circuit. The first-stage gain circuit is coupled to the feedback circuit, and the feedback circuit generates a zero-point at the output end of the first-stage gain circuit.

Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths to provide variable gain for individual amplifier inputs. The variable gain for an individual input is provided using a amplification stage that is common for each input of the amplifier. A variable attenuation is provided for individual inputs through a combination of a band selection switch and an attenuation selection branch. The attenuation can be tailored for individual inputs and can depend on a gain mode of the amplifier.

The present invention discloses a signal output circuit having DC gain maintaining mechanism used in an image signal transmission apparatus that includes a front-stage driving circuit and a back-stage driving circuit. The front-stage driving circuit includes a continuous time linear equalizer (CTLE) having an adjusting capacitor and configured to receive a digital input signal to perform a high frequency enhancement thereon to increase a bandwidth of the digital input signal to generate a front-stage output signal. The back-stage driving circuit includes a CTLE without the adjusting capacitor and configured to increase a DC gain of the front-stage output signal to compensate a DC gain drop between the front-stage output signal and the digital input signal to generate a back-stage output signal to an image signal receiving apparatus.

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

Low-noise amplifier having programmable-phase gain stage. In some embodiments, a radio-frequency amplifier can include an input node, an output node, and a programmable-phase gain stage implemented between the input node and the output node. The programmable-phase gain stage can be configured to operate in one of a plurality of gain settings, and to provide a desired phase for a signal at each of the plurality of gain settings.

A signal amplifier having an input impedance that varies over different bias currents, the signal amplifier comprising a compensation stage including a switchable variable resistance configured to provide a targeted adjustment to the input impedance. A signal amplifier comprising: a variable-gain stage configured to provide a plurality of gain levels that result in different input impedance values; and a compensation stage having a switchable variable resistance configured to provide a targeted adjustment to a respective input impedance. a compensation stage having an output coupled to an input of the gain stage, the compensation stage including a plurality of band selection switches coupled to the plurality of input nodes and a plurality of switchable variable resistance branches coupled to the band selection switches, individual switchable variable resistance branches configured to provide a targeted adjustment to a respective input impedance.

Disclosed herein are signal amplifiers that provide impedance adjustments for different gain modes. The impedance adjustments are configured to result in a constant real impedance for an input signal at the amplifier. The amplifiers include a scalable impedance adjustment circuit that adjusts inductance and/or a device width to compensate for changes in the total impedance presented to an input signal. By providing impedance adjustments, the amplifiers reduce losses and improve performance by improving impedance matching over a range of gain modes.

Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths that allow signals in a high gain mode to bypass attenuation. This advantageously reduces or eliminates performance penalties in the high gain mode. The programmable attenuators can be configured to improve linearity of the amplification process through pre-LNA attenuation in targeted gain modes. In addition, described herein are variable gain amplifiers with embedded attenuators in a switching network. The attenuators can be embedded onto switches and can be configured to have little or no effect on a noise factor in a high gain mode because the switching network can provide an attenuation bypass in a high gain mode and an attenuation in other gain modes. The programmable attenuators can be embedded onto a multi-input LNA architecture.

A digitally controlled amplifier (DCA) has a drive (e.g., bipolar junction) transistor with a base to accept an input signal and a collector to supply an output signal. The DCA also includes n switchable gain amplifier networks (SGANs). Each SGAN has a signal input connected to the collector of the drive transistor, an input to accept a logic signal, and a signal output to supply a switchable gain AC output signal to a load in response to the logic signal. The SGAN signal outputs are connected together, typically in parallel, to supply a digitally controlled AC output gain. An auxiliary SGAN may be connected to supply a constant gain AC output signal. Each of the SGANs may have an identical switchable AC gain and accept an independent logic signal to supply (n+1) levels of digitally controlled AC output gain.