A surface acoustic wave device is disclosed. The surface acoustic wave device can include a support substrate structure, a first piezoelectric layer over the support substrate structure, and a second piezoelectric layer over the first piezoelectric layer. The second piezoelectric layer has a first region with a first thickness and a second region with a second thickness different from the first thickness. The surface acoustic wave device can include a first acoustic wave element that is positioned in the first region, and a second acoustic wave element that is positioned in the second region.

In an elastic wave device, a piezoelectric substrate is stacked on a support substrate and an IDT electrode is provided on the piezoelectric substrate. Wiring line portions are provided on the piezoelectric substrate. A first hollow portion is provided in the support substrate at least below at least one of the wiring line portions and or below a region between the wiring line portions.

An electronic component includes first and second element substrates, first and second functional element portions, and a support layer that defines a first hollow space over a first functional electrode with the first and second element substrates. A second functional electrode is located on a first main surface of the second element substrate. The electronic component further includes a first conductive layer that is provided on a second main surface of the second element substrate and that is connected to ground potential. The first conductive layer opposes the first functional electrode in the first hollow space. The first conductive layer is overlapped with at least a portion of the first and second functional electrodes in a plan view.

A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.

A surface acoustic wave device includes: a pair of comb-type electrodes that are provided on a piezoelectric substrate and include electrode fingers and dummy electrode fingers, the electrode fingers of one of the pair of comb-type electrodes facing the dummy electrode fingers of the other comb-type electrode; and additional films that are provided to cover gaps between tip ends of the electrode fingers and tip ends of the dummy electrode fingers and to overlap with at least one of first through third groups in which the first and second groups respectively include the electrode fingers and the dummy electrode fingers located at opposite sides of the gaps in a first direction in which the electrode fingers extend, and the third group includes the electrode fingers located at sides of the gaps in a second direction that crosses the first direction.

The disclosure provides a method for assembling and interconnecting FBAR filter and an electronic device. The method includes constructing an equivalent circuit model of an assembled FBAR filter according to a circuit model of a filter chip and the grounding circuit of the FBAR filter; modeling, simulating and calculating the grounding circuit to extract parasitic parameters corresponding to the grounding pad and a grounding bond-wire of the grounding circuit, respectively; feedbacking the parasitic parameters back into the equivalent circuit model, and using the circuit simulation software to obtain an S parameter of the filter; adjusting the parasitic parameters of the grounding circuit to optimize an S parameter performance of the FBAR filter: obtaining an optimal assembly configuration of the FBAR filter to guide the assembly. The parasitic parameters include a parasitic inductance of the grounding bond-wire and a parasitic capacitance and parasitic inductance of the grounding pad.

A method of fabricating a bonded wafer with low carrier lifetime in silicon comprises providing a silicon substrate having opposing top and bottom surfaces, modifying a top portion of the silicon substrate to reduce carrier lifetime in the top portion relative to the carrier lifetime in portions of the silicon substrate other than the top portion, bonding a piezoelectric layer having opposing top and bottom surfaces separated by a distance T over the top surface of the silicon substrate, and providing a pair of electrodes having fingers that are inter-digitally dispersed on a top surface of the piezoelectric layer, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device. The modifying and bonding steps may be performed in any order. The modified top portion of the silicon substrate prevents the creation of a parasitic conductance within that portion during operation of the SAW device.

A bonded wafer with low carrier lifetime in silicon comprises a silicon substrate having opposing top and bottom surfaces, the structure of the silicon in a top portion of the silicon substrate having been modified to reduce the carrier lifetime in the top portion relative to the carrier lifetime in portions of the silicon substrate other than the top portion; a piezoelectric layer bonded over the top surface of the silicon substrate and having opposing top and bottom surfaces separated by a distance T; and a pair of electrodes having fingers that are inter-digitally dispersed on the top surface of the piezoelectric layer in a pattern having a center-to-center distance D between adjacent fingers of the same electrode, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device. Modification of the top portion of the silicon substrate prevents the creation of a parasitic conductance within the top portion of the silicon substrate during operation of the SAW device.

A piezoelectric-on-insulator substrate comprises a support substrate having a first acoustic impedance, a piezoelectric layer, especially a layer of lithium tantalate, lithium niobate, aluminum nitride, lead zirconate titanate, langasite or langatate, a dielectric layer having a second acoustic impedance and sandwiched between the piezoelectric layer and the support substrate, an intermediate layer positioned between the support substrate and the dielectric layer. The intermediate layer is a layer having a variable composition, in particular along its thickness, such that the acoustic impedance of the intermediate layer varies, in particular gradually, between the values of the first and the second acoustic impedances. The present disclosure also relates to a method for producing such a piezoelectric-on-insulator substrate and also to a surface acoustic wave device comprising such a piezoelectric-on-insulator substrate.

A piezoelectric-on-insulator (POI) substrate comprises: a carrier substrate, in particular, a substrate based on silicon; a piezoelectric layer, in particular, a layer of lithium tantalate or of lithium niobate; a dielectric layer, in particular, a layer of silicon oxide, sandwiched between the piezoelectric layer and the substrate; a trapping structure sandwiched between the dielectric layer and the carrier substrate. The trapping structure comprises at least two trapping layers, which layers are separated each time by a dielectric intermediate layer. A method is used for producing such a piezoelectric-on-insulator substrate.