A signal processing circuit with high noise resistance is realized. The signal processing circuit includes: a first pre-stage circuit that includes a first input terminal; and a second pre-stage circuit that includes a second input terminal. A resistive element with one end connected to the first input terminal and a capacitative element with one electrode connected to the ground are provided in the first pre-stage circuit. The other end of the first resistive element and the other electrode of the first capacitative element are connected to each other. An output node of the first pre-stage circuit and an output node of the second pre-stage circuit are connected to a post-stage circuit.

A signal processing circuit with high noise resistance is realized. The signal processing circuit includes: a first pre-stage circuit that includes a first input terminal; and a second pre-stage circuit that includes a second input terminal. A resistive element with one end connected to the first input terminal and a capacitative element with one electrode connected to the ground are provided in the first pre-stage circuit. The other end of the first resistive element and the other electrode of the first capacitative element are connected to each other. An output node of the first pre-stage circuit and an output node of the second pre-stage circuit are connected to a post-stage circuit.

The ABB blocks 332, 334, 336, and 318 are configured to process the I/Q signals corresponding to the first or the second HB independently or the I/Q signals corresponding to the LB in cooperation by two. In detail, the first ABB I block 332 and the first ABB Q block 334 operate independently in the 3G/4G mode but they are configured to process the I signal (or Q signal) of the LB in the 2G mode. Likewise, the second ABB Q block 336 and the second ABB I block 318 operate independently in the 3G/4G mode but they are configured to process the Q signal (or I signal) of the LB in the 2G mode. The first ABB I/Q blocks 332 and 334 and the second ABB I/Q blocks 336 and 318 are arranged symmetrically to processing the I/Q signals cooperatively in the 2G mode. In detail, the second ABB Q block 336 is arranged close to the first ABB Q block 334 such that the capacitor regions included in the first ABB I/Q blocks 332 and 334 are connected to each other and the capacitor regions included in the second ABB I/Q blocks 336 and 338 are connected to each other.