One example includes a digital signal conditioner (DSC) system. A sample selector bank receives a digital sample block of an input signal that is provided at a supported input oversampling factor and selects a subset of samples from the digital sample block based on a selection signal. A tap weights selector bank generates a set of tap weights based on the selection signal. A filter bank receives the subset of the samples from each of the sample selectors and a respective set of tap weights. Each filter provides a weighted sample associated with the respective subset of samples and the respective set of tap weights. A reformattor receives the weighted sample from each of the filters and provides a filtered sample block including the weighted sample from a subset of the filters at an output oversampling factor for each supported input oversampling factor based on a selected supported resampling ratio.

Highly efficient digital domain sub-band based receivers and transmitters.

A transmitter module for a broadband data transmission system for radio communications, comprising at least one polyphase FFT filter bank is described. The at least one polyphase FFT filter bank is established as a synthesis polyphase FFT filter bank, wherein the at least one polyphase FFT filter bank comprises several filter units, wherein the transmitter module is configured to receive an input signal comprising a symbol sequence, and wherein the transmitter module is configured to transmit a signal based on the received input signal. Moreover, a receiver module for a broadband data transmission system and a data transmission system are described.

Systems and methods are provided for channelizing. A first stage can provide a WOLA filter bank that can apply a single multiplier resource to perform window weighting for multiple WOLA filter banks. The first stage can remove mixer-based post FFT adjustment and provide equal functionality with a particular modification of tuning mixers at inputs of second stage FIR paths. The first stage can include a variable decimation, using a particular implementation of variable sample block size.

System and method for identifying an RF emitter include: channelizers for channelizing RF signals into several channels; a compressive sensing (CS) encoder for each channel to CS encode the channelized signal to produce an encoded channelized signal in each of the plurality of channels; a summer to sum the encoded channelized signals of all of the plurality of channels to produce an I/Q data; a channelized pulse detection circuit to detect pulses in each channel and produce encoded pulse snippets from the I/Q data; a CS decoder for each channel to CS decode the encoded pulse snippets; a first machine learning device to characterize the decoded pulse snippets and to produce pulse description words (PDWs); and a second machine learning device to associate the PDWs with one or more RF emitters and identify the one or more RF emitters.

Systems and methods are provided for channelizing. A first stage can provide a WOLA filter bank that can apply a single multiplier resource to perform window weighting for multiple WOLA filter banks. The first stage can remove mixer-based post FFT adjustment and provide equal functionality with a particular modification of tuning mixers at inputs of second stage FIR paths. The first stage can include a variable decimation, using a particular implementation of variable sample block size.

In one aspect, a computer-implemented method includes receiving a signal corresponding to electrical activity of a patient's heart; separating the signal into component signals; detecting fractional phase transitions for each of the component signals; generating, at each of the detected fractional phase transitions for each of the component signals, a data object containing a time value and an amplitude value; for a set of consecutive data objects associated with a first component signal of the component signals, detecting a peak amplitude; for a set of consecutive data objects associated with a second component signal of the component signals, detecting a peak amplitude; determining that the peak amplitudes satisfy a first time; calculating a consolidated peak amplitude and a consolidated peak time; and in response to determining that the consolidated peak amplitude satisfies both an amplitude criterion and a second time criterion, providing an indication of a detected heartbeat.

The present invention proposes a new method for improving the performance of a real-valued filterbank based spectral envelope adjuster. By adaptively locking the gain values for adjacent channels dependent on the sign of the channels, as defined in the application, reduced aliasing is achieved. Furthermore, the grouping of the channels during gain-calculation, gives an improved energy estimate of the real valued subband signals in the filterbank.

The implementation of modal processors, which involve the parallel combination resonant filters, may be costly for applications such as artificial reverberation that can require thousands of modes. In one embodiment, the input signal is decomposed into a plurality of subbands, the outputs of which are downsampled. In each downsampled band, resonant filters are applied at the downsampled sampling rate, and their output is upsampled and filtered to form the band output.

A 1st frequency reduction circuit of a filter of the invention downsamples the sampling rate of a signal source to a predetermined value to obtain a 1st PCM stream, a 1st frequency raising circuit raises the sampling rate of the 1st PCM stream to be the same as that of the signal source, a 1st delay circuit delays a stream of the signal source, such that its phase is the same as that of the 1st PCM stream, a 1st adder subtracts the frequency raised 1st PCM steam from the delayed stream of the signal source to obtain a passband 1, a j-th frequency reduction circuit downsamples the sampling rate of a (j1)-th PCM stream to a predetermined value to obtain a j-th PCM stream, wherein 2jn, a j-th frequency raising circuit raises the sampling rate of the j-th PCM stream to be the same as that of the (j1)-th PCM stream, a j-th delay circuit delays the (j1)-th PCM stream, such that its phase is the same as that of the j-th PCM stream, a j-th adder subtracts the frequency raised j-th PCM stream from the delayed (j1)-th PCM stream to obtain a passband j, and when j=n, the j-th PCM stream is a passband n+1.