A measuring arrangement acquires signals of alternating electrical magnitudes. A sampling apparatus performs a sampling of the signals to form digital sample values. A clock tracking apparatus adapts a sampling clock used by the sampling apparatus in the light of the frequency of the signal to be sampled. In order to be able to acquire reliably signals of alternating electrical magnitudes even when they have different frequencies, the sampling apparatus samples at least two of the signals each with its own sampling clock and the clock tracking apparatus adapts the sampling clock in the light of the frequency of the signal to be sampled simultaneously for each of these at least two signals. There is also described a corresponding method for measuring electrical signals.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Deterioration in audio quality is inhibited in a device which records audio and stretches a reproduction time period. A sampling processing unit performs processing of sampling audio in a predetermined period at a sampling rate higher than a predetermined sampling rate to generate audio data as high-resolution audio data, and processing of sampling audio outside the predetermined period at the predetermined sampling rate to generate audio data as normal audio data. Also, a reproduction time conversion unit stretches the reproduction time period of the high-resolution audio data.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Deterioration in audio quality is inhibited in a device which records audio and stretches a reproduction time period. A sampling processing unit performs processing of sampling audio in a predetermined period at a sampling rate higher than a predetermined sampling rate to generate audio data as high-resolution audio data, and processing of sampling audio outside the predetermined period at the predetermined sampling rate to generate audio data as normal audio data. Also, a reproduction time conversion unit stretches the reproduction time period of the high-resolution audio data.

Provided, among other things, is an apparatus for digitally processing a discrete-time signal that includes: an input line for accepting an input signal, processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. First and second lowpass filters, each having a frequency response with a magnitude that varies approximately with frequency according to a product of raised functions, are included within baseband processors in such processing branches.

Provided, among other things, is an apparatus for digitally processing a discrete-time signal that includes: an input line for accepting an input signal, processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. First and second lowpass filters, each having a frequency response with a magnitude that varies approximately with frequency according to a product of raised functions, are included within baseband processors in such processing branches.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Control unit (100) for a transmission system, comprising: a sample rate converter (10), which is coupled to a digital-to-analog converting unit (200), wherein digital input data (data_in) are feedable to the sample rate converter (10); a PRBS generator (20), wherein an output signal (ss_div) of the PRBS generator (20) is feedable to the sample rate converter (10) and to a delay element (30), wherein an output signal (ss_div_del) of the delay element (30) is feedable to a frequency synthesizer (40), wherein the frequency synthesizer (40) is clockable by a reference clock (clk_ref) and wherein an output signal (clk_ss) of the frequency synthesizer (40) is feedable to a clock input (10a) of the sample rate converter (10) and to a clock input (200a) of the digital-to-analog converting unit (200).

A system for processing audio data includes an isochronous data interface to output a first stream of audio data, a plurality of output sample rate converters to output a second stream of audio data, a plurality of transaction control registers to control routing of the first stream of audio data between the isochronous data interface and an output sample rate converter of the plurality of output sample rate converters, a processor to remove first header data from the first stream of audio data output from the isochronous data interface and to write the first header data to a circular buffer, a first audio header register to control forwarding of the first header data for prepending to the second stream of audio data output by the plurality of output sample rate converters, and a plurality of output control registers to control write enables of the plurality of output sample rate converters.