Provided is a relaxation oscillator that is very small in temperature deviation of an oscillation period. The relaxation oscillator includes an oscillation circuit, a variable frequency divider, and a counter. The oscillation circuit is configured to switch between a first clock signal having a negative value as a first-order temperature coefficient of an oscillation period, and a second clock signal having a positive value as a first-order temperature coefficient of an oscillation period, based on a signal from the counter, and to output the switched-to clock signal as a third clock signal. The variable frequency divider is configured to divide the frequency of the third clock signal that is output from the oscillation circuit, and to output the frequency-divided third clock signal as a clock signal. The counter is reset by the clock signal.

Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

A device includes a capacitor having a first terminal coupled to a ground node, and a second terminal; a first transistor having a source coupled to the capacitor, a drain coupled to a first node, and a gate; a first current source coupled to the first node and configured to couple to a regulated supply node; a second transistor having a source coupled to the ground node, a drain coupled to a second node, and a gate coupled to the second node and to the gate of the first transistor; and a comparator circuit having an input coupled to the first node and an output configured to couple to a clock node.

Provided is a relaxation oscillator that is very small in temperature deviation of an oscillation period. The relaxation oscillator includes an oscillation circuit, a variable frequency divider, and a counter. The oscillation circuit is configured to switch between a first clock signal having a negative value as a first-order temperature coefficient of an oscillation period, and a second clock signal having a positive value as a first-order temperature coefficient of an oscillation period, based on a signal from the counter, and to output the switched-to clock signal as a third clock signal. The variable frequency divider is configured to divide the frequency of the third clock signal that is output from the oscillation circuit, and to output the frequency-divided third clock signal as a clock signal. The counter is reset by the clock signal.

The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

Provided is a relaxation oscillator having an extremely small temperature deviation in oscillation frequency. A first current (I1) generated by a reference voltage source and a first resistor having a positive first-order temperature coefficient is supplied to a first variable capacitor (C1) for oscillation, and a second current (I2) generated by a reference voltage source and a second resistor having a negative first-order temperature coefficient is supplied to a second variable capacitor (C2) for oscillation. A product of a value of a ratio of a first current to a second current and a value of a ratio of a first-order temperature coefficient of the second resistor to a first-order temperature coefficient of the first resistor, and a value of a ratio of a capacitance of the first variable capacitor to a capacitance of the second variable capacitor have the same absolute value and opposite signs.

A built-in self-test (BIST) methodology and apparatus provide for testing and calibration of an integrated circuit oscillator circuit topology that uses a one-pin (a single-pin) external resonator. The method employs dedicated test circuitry, also referred to herein as BIST apparatus, for the pass/fail verification of both the active and passive building blocks of the oscillator. At the same time, the methodology ensures accurate calibration and matching of the capacitors using dedicated digital circuitry and algorithms.