Disclosed is a method for synchronising at least one slave control circuit, controlled by a slave control signal having pulse width modulation, with a master control circuit, controlled by a master control signal having pulse width modulation, including the following steps: the master control circuit emitting a synchronisation signal indicating a master edge of an electrical quantity; the slave control circuit receiving the synchronisation signal; measuring a delay between a slave edge of the same electrical quantity and the master edge of the electrical quantity; time-shifting the slave control signal so as to reduce the delay; and repeating the measurement step until the delay is eliminated.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

A pull-up voltage detection circuit is for use in a serial bus. The serial bus includes a communication signal. During a communication interval, the communication signal is toggled based on a pull-up voltage for communicating on the serial bus via open-drain scheme. The pull-up voltage detection circuit includes: at least one comparator circuit for comparing the communication signal or a divided voltage thereof with at least one reference voltage in a detection procedure, so as to generate at least one comparison result; and a selector circuit for selecting one of plural predetermined voltages according to the at least one comparison result. The selected predetermined voltage serves as a logic threshold voltage corresponding to the pull-up voltage. In the communication interval, the logic state of the communication signal is determined by comparing the communication signal and the logic threshold voltage for communicating on the serial bus.

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series.

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

Disclosed is a method for synchronising at least one slave control circuit, controlled by a slave control signal having pulse width modulation, with a master control circuit, controlled by a master control signal having pulse width modulation, including the following steps: the master control circuit emitting a synchronisation signal indicating a master edge of an electrical quantity; the slave control circuit receiving the synchronisation signal; measuring a delay between a slave edge of the same electrical quantity and the master edge of the electrical quantity; time-shifting the slave control signal so as to reduce the delay; and repeating the measurement step until the delay is eliminated.

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.