A clock generator circuit includes an internal reference clock generator, a sequential circuit, and a pulse generator circuit. The internal reference clock generator circuit receives a clock buffer signal, a reset signal, and provides a first clock signal. The sequential circuit receives the first clock signal, and provides an internal reference clock signal based on the first clock signal. The pulse generator circuit receives the internal reference clock signal, a slow ring oscillator clock signal, and the reset signal. The pulse generator circuit counts a number of internal reference clock signals cycles for each cycle of the slow ring oscillator clock signal, and generates a pulse signal in response to the number being equal to zero during a cycle of the slow ring oscillator clock signal. The pulse signal toggles the flip-flop clock circuit to recover from a deadlock.

A level shifter includes a level switching circuit, an input circuit, and a first voltage drop circuit. The level switching circuit is configured to adjust a first voltage level of a first node and a second voltage level of a second node in response to a first input signal and a second input signal. The input circuit is configured to receive the first input signal and the second input signal. The first voltage drop circuit is coupled between the level switching circuit and the input circuit, and is configured to track a voltage level of a third node which is coupled to the first node, in order to be turned on according to the voltage level of the third node.

Exemplary embodiments are directed to power path switching between multiple charging ports of an electronic device. A device may include a charging port of a plurality of charging ports for coupling to a power supply via an over-voltage protection circuit. The device may further including a comparison unit configured to couple the charging port to the power supply based at least partially on a comparison between a voltage at an input of the over-voltage protection circuit coupled to the charging port with a voltage at the output of the over-voltage protection circuit coupled to the power supply.

The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

Certain aspects are directed towards an interpolator and/or a clock generator. An example interpolator generally includes: a first capacitive element; a first current source; a first switch coupled between the first capacitive element and the first current source; a second current source; a second switch coupled between the first capacitive element and the second current source; and a first comparison circuit having an input coupled to the first capacitive element.

For example, a signal transmission device includes a transmitter provided in a primary circuit system and configured to generate a transmission signal according to an input signal; at least one first isolating element configured to constitute a first signal transmission path for transmission of the transmission signal from the primary circuit system to the secondary circuit system; at least one second isolating element configured to constitute a second signal transmission path, different from the first signal transmission path, for transmission of the transmission signal from the primary circuit system to the secondary circuit system; and a receiver provided in the secondary circuit system and configured to feed a first reception signal and a second reception signal output respectively from the first and second isolating elements to a logic circuit to generate a single output signal.