A method for unbalancing a tri-level switching regulator uses hysteretic control when switching across multiple states of the tri-level switching regulator. The method includes determining a battery voltage and an output voltage of the tri-level switching regulator. The method also includes dynamically adjusting at least one of a first hysteretic window of a first hysteretic comparator associated with a second switching state of the tri-level switching regulator and a second hysteretic window of a second hysteretic comparator associated with a first switching state of the tri-level switching regulator based on the battery voltage and the output voltage.

A single-ended or differential level-shifting interface for GaN ICs that allows GaN ICs to be controlled with standard low-voltage CMOS level inputs. The logic level shift circuit is based on a resistive network is therefore insensitive to process and temperature variations, making it particularly well suited for implementation in a GaN IC. The resistive network for a single-ended input signal includes a first branch with a voltage divider connected to the input signal. The voltage divider of the first branch provides a level shifted and scaled input signal to the first input of a comparator at the optimal bias point of the comparator. The resistive network also includes a second voltage divider branch with hysteresis for providing a trip voltage to the second input to the comparator, also at the optimal bias point of the comparator. The comparator outputs complementary bipolar level shifted signals corresponding to the input signal.

A DC-DC converter includes an output terminal, a reference voltage source, an error amplifier, and a compensation circuit. The error amplifier is coupled to the output terminal and the reference voltage source. The error amplifier is configured to generate an error signal representative of a difference between a voltage at the output terminal and a reference voltage provided by the reference voltage source. The compensation circuit is coupled to the error amplifier. The compensation circuit includes a resistor, a capacitor, and a switch control circuit. The resistor is coupled to the error amplifier. The capacitor is coupled to the resistor. The switch control circuit is configured to modulate connection of the resistor to the capacitor based on a switching frequency of the DC-DC converter.

This application relates an activity detector (100) for detecting signal activity in an input audio signal (S.sub.IN), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) 101 including a first hysteretic comparator (201) for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM (103) having a second hysteretic comparator (401) is arranged to receive a reference voltage (V.sub.MID) and generate a clock signal (S.sub.CLK). A time-decoding converter (102) receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor (104) is responsive to a count signal (S.sub.CT) from the TDC 102 to determine whether the input audio signal comprises signal activity above a defined threshold.

A hysteresis control method for inverter and an inverter based on hysteresis control are disclosed. The inverter is electrically connected to a power grid, and the method includes: Step S1, sampling a grid voltage V.sub.g(z) and an output current I.sub.g(z) of the inverter; Step S2, calculating a present period hysteresis bandwidth H(z) based on the grid voltage V.sub.g(z) sampled in step S1; Step S3, predicting a next period hysteresis bandwidth H(z+1); Step S4, correcting the present period hysteresis bandwidth H(z) based on the next period hysteresis bandwidth H(z+1) obtained in step S3, to obtain a final hysteresis bandwidth H.sub.out(z); and Step S5, controlling an output driving signal according to the output current I.sub.g(z) of the inverter and the final hysteresis bandwidth H.sub.out(z) to control the operation of the inverter.

A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

An electronic fuse for a power supply includes at least two switching elements and a regulation unit, wherein a first switching element is arranged in a main branch, where the regulation unit is switches off the first switching element when a predetermined threshold value is exceeded by a prevailing current value, and a second switching element that is also actuated by the regulation unit, which is arranged in an auxiliary branch parallel to the first switching element and assumes a substantial proportion of a resulting power loss when an overload occurs, and the second switching element, which is arranged in at least one auxiliary branch, is configured or optimized for linear operation, and where the at least two switching elements are configured such that the line resistance of the second switching element is at least twice the line resistance of the first switching element.

A capacitive-coupled level shifter includes a capacitive divider circuit having a first capacitive divider branch configured to couple a first input terminal to a first comparator terminal and a second capacitive divider branch configured to couple a second input terminal to a second comparator terminal. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of a modulated signal input to the capacitive divider circuit. A level shifter system which includes the capacitive-coupled level shifter is also described.

In an example embodiment, a universal serial bus (USB) Type-C controller comprises a current detector circuit configured to provide over-current protection on a voltage bus (VBUS) line. The current detector circuit comprises a current sense amplifier, a reference voltage generator, and a comparator coupled to the current sense amplifier and to the reference voltage generator. The current sense amplifier is configured to receive a pair of input voltages from the VBUS line and to output an indicator signal responsive to an input voltage difference between the pair of input voltages. The reference voltage generator is configured to generate a reference voltage in response to a voltage selector signal. The comparator is configured to output an interrupt signal responsive to the indicator signal exceeding the reference voltage.