Comparison circuit and delay cancellation method are provided. The circuit includes a control circuit, capacitors and a transconductance amplifier circuit, wherein the control unit is configured to receive an input signal and control the comparison circuit to be in different working stages; the capacitors are configured to store a DC offset voltage signal at an automatic zero calibration stage; store the input signal when the output signal is inverted at a measurement stage; and store an equivalent delay voltage signal at a delay sampling stage; the transconductance amplifier circuit is configured to store the DC offset voltage signal to the capacitors at the automatic zero calibration stage; compare voltage signals on positive and negative input terminals and generate an output signal at the measurement stage; and store the equivalent delay voltage signal to the capacitors at the delay sampling stage. An inherent delay of the comparison circuit may be cancelled.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

In an example embodiment, a universal serial bus (USB) Type-C controller comprises a current detector circuit configured to provide over-current protection on a voltage bus (VBUS) line. The current detector circuit comprises a current sense amplifier, a reference voltage generator, and a comparator coupled to the current sense amplifier and to the reference voltage generator. The current sense amplifier is configured to receive a pair of input voltages from the VBUS line and to output an indicator signal responsive to an input voltage difference between the pair of input voltages. The reference voltage generator is configured to generate a reference voltage in response to a voltage selector signal. The comparator is configured to output an interrupt signal responsive to the indicator signal exceeding the reference voltage.

An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.

A circuit for detecting a signal disturbance comprising a high-pass filter, a comparator, an asynchronous counter, a synchronizer, and processing circuitry. The high-pass filter is configured to generate a filtered signal from a monitored signal. The comparator is configured to generate a compare result signal based on a comparison of the filtered signal and a threshold reference. The asynchronous counter is configured to generate a count value of threshold crossings based on the compare result signal. The synchronizer is configured to generate a synchronous output signal for storage at digital memory that is based on the count signal value. The processing circuitry is configured to determine that a disturbance has occurred at the monitored signal based on the synchronous output signal.

Provided is a reverse current switch. The reverse current switch includes: a comparison unit including a first input end, a second input end, and a first output end; and a switch resistance unit, where a first end of the switch resistance unit is connected to the first input end, a second end of the switch resistance unit is connected to the second input end, and a third end of the switch resistance unit is connected to the output end of the comparison unit, and the switch resistance unit is controlled by a voltage of the first output end. This reverse current switch has a simple structure and can implement working under low voltage conditions.

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (701) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK.sub.1).

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

An operational amplifier-based hysteresis comparator and a chip are provided. The hysteresis comparator includes: an input stage and an amplification stage. The input stage includes: a first input branch and a second input branch, where the first input branch generates a first current based on the first voltage, and the second input branch generates a second current based on the second voltage. The first current is connected with a first input terminal of the amplification stage, and the second current is connected with a second input terminal of the amplification stage. An output terminal of the amplification stage outputs a first level when the first current is greater than the second current, and outputs a second level when the first current is less than the second current. The present disclosure changes the hysteresis voltage generation mode, thereby reducing the instability caused by positive feedback.

An apparatus for self-calibration in isolated communication is included. A plurality of integrated circuits perform isolated communication with respect to each other. A microcomputer is configured to output a self-calibration instruction to the plurality of integrated circuits when a predetermined condition is met or in response to at least one of a periodic instruction or an aperiodic instruction. A plurality of processors are respectively provided in a corresponding one of the plurality of integrated circuits. Each of the processors being configured to perform a self-calibration operation to transmission parts and receiving parts in the corresponding integrated circuit.