Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Methods, systems, and computer readable media described herein can be operable to facilitate transitioning a device from a first state to a second state. A switch described herein allows for the use of an electronic circuit to perform the toggle and persistence functions while simultaneously giving more flexibility to the industrial design and physical switch implementation. The switch allows this preserving of the state using only a toggle on a voltage and thus allowing for a hardware only solution. The switch described herein allows for the use of smaller and less complicated mechanical switches allowing for more compact industrial designs. The switch uses a programmable voltage reference as a 1 bit non-volatile memory cell that is programmed by means of a logic pulse to the device. This allows a software independent setting of the state of the privacy switch. This state will remain through power cycles.

The present disclosure relates to a high speed, differential input, single phase clock circuit. The circuit may include a cross-coupled PMOS connected with a cross-coupled NMOS via a pass gate. The circuit may further include a single-phase clock in communication with the cross-coupled PMOS and the cross-coupled NMOS. The circuit may also include a master and a slave each having an output node that charges and discharges to V.sub.DD or ground respectively, wherein there is no direct feedback from an output of the circuit to an input the circuit and there is no precharged state in the circuit.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

A clocked storage element comprises a first latch having an input data node, a clock input node and a first latch output data node, and a second latch having an input connected to the first latch output data node, a clock input node and a second latch output data node. The first and second latches can have a clocked pull-up current path consisting of two p-channel transistors between their respective output data nodes and the VDD supply line, and a clocked pull-down current path consisting of two n-channel transistors between their respective output data nodes and the VSS supply line.

A data retention circuit is provided in the invention. The data retention circuit includes a master latch circuit, a slave latch circuit, and a control circuit. The control circuit is coupled to the master latch circuit and the slave latch circuit and receives a clock signal from a clock circuit and a power management signal from a power management unit (PMU). In a normal operation mode, the control circuit transmits the clock signal to the master latch circuit and the slave latch circuit. In sleep mode, power to the master latch circuit is switched off and the control circuit transmits the power management signal to the slave latch circuit.

An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Circuits, systems, and methods are described herein for generating master clock signals and slave clock signals for controlling a flip-flop having a master latch and a slave latch. A circuit includes a master latch configured to latch an input data signal and to output a data latch signal based on a master clock signal. The circuit also includes a slave latch coupled to the master latch and configured to generate an output data signal based on a slave latch clock signal and the data latch signal. Additionally, the circuit includes a skewed clock circuit coupled to the master latch and the slave latch. The skewed clock circuit is configured to receive a clock signal and generate the master clock signal and the slave clock signal based on the clock signal. The master clock signal and the slave clock signal are independent clock signals whose timing is skewed relative to one another by the skewed clock circuit.

A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.