An aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Per another aspect, the apparatus includes additional circuitry to allow the apparatus to process signals in accordance with a third voltage domain.

A semiconductor device includes an output control circuit configured to generate a pre-output control signal and an output control signal according to the number of times that an output strobe pulse is inputted. The semiconductor device also includes a pipe circuit configured to generate latched data by latching input data on the basis of an input control signal, select some bits of the bits of the latched data and set the selected bits to pre-output data on the basis of the pre-output control signal, and output the pre-output data as output data on the basis of the output control signal.

Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.

Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.

A multi-clock domain system includes a synchronizer circuit. The synchronizer circuit includes a sequential logic circuit and a synchronizing stage. The sequential logic circuit receives a functional signal that is generated based on a first clock signal that is further associated with a first clock domain, a second clock signal that is associated with a second clock domain, and a reference signal. Based on the first and second clock signals and the reference signal, the synchronizer circuit outputs a logic signal. When the functional signal is activated, the logic signal is activated and remains activated for a predetermined time duration after the functional signal is deactivated. The synchronizing stage receives the second clock signal and further receives the logic signal from the sequential logic circuit, and outputs a synchronized functional signal.

A register with data retention includes a master-slave flip-flop, a balloon latch, and a level shifter. The master-slave flip-flop is supplied by a first power voltage. The balloon latch is supplied by a second power voltage. The second power voltage is independent of the first power voltage. The level shifter provides a voltage conversion between the master-slave flip-flop and the balloon latch. A data is stored in the master-slave flip-flop. When the first power voltage is disabled, the balloon latch is configured to temporarily retain the data.

A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.

Memory devices receive a data signal and an accompanying data strobing signal, which informs the device that data is ready for latching. The data strobing signal enables capturing the data while the data signal transitions from a logic high to a logic low or vice versa, resulting in an indeterminate output (e.g., between 0 and 1). The indeterminate value may cause metastability in memory operations using the indeterminate output. To prevent or reduce metastability, a cascaded timing arbiter latch includes cascaded alternating NAND timing arbiters and NOR timing arbiters. In some embodiments, these logic gates are connected to transistors above and below the cascaded timing arbiters. The cascaded timing arbiters and/or transistors provide amplification on a feedback path of the latch. In other embodiments, the cascaded timing arbiters are isolated by inverters and are not connected to transistors. This embodiment reduces capacitive loading on nodes of the internal feedback path.

A processing circuit includes an input circuit and a follow-up circuit. The input circuit includes a first transistor, a second transistor, and a delay element. The first transistor has a control terminal, a first connection terminal, and a second connection terminal. The control terminal of the first transistor is arranged to receive a data signal. A first connection terminal of the second transistor is coupled to the second connection terminal of the first transistor, and a control terminal of the second transistor is arranged to receive a first non-data signal. The delay element is coupled between the control terminal and the second connection terminal of the first transistor. A data input is received at an input node of the follow-up circuit, and the input node of the follow-up circuit is coupled to the second connection terminal of the second transistor.

A retention mode sequential logic circuit has no balloon latch, and all its P-channel transistors are disposed in a single N-well. In one example, the circuit is a retention flip-flop that has an active high retention signal input and an active low reset input. In another example, the circuit is a retention flip-flop that has an active low retention signal input and an active low reset input. In a multi-bit retention register example, one common clock and reset signal generation logic circuit drives multiple pairs of latches. Each retention mode logic circuit described has a low transistor count, is implemented with a single N-well, exhibits low retention mode power consumption, is not responsive to a reset signal in the retention mode, and has a fast response time when coming out of retention mode operation.