An electronic system for triggering and transporting conditional information from a user or an item, the system comprising at least one each of electronic circuit, carrier, rectifier, buffer, source, level shifter, system clock, sync unit, communication unit, interpreter and/or bidirectional interface; a set of electrodes for recognizing 3D-gestures of a user and at least one bidirectional integrated display, wherein sync unit synchronizes the electronic circuit with the source by briefly (e.g. for 1 millisecond) interrupt alternating electric charges and/or sound waves and/or vibrations, and/or also reacts to changes caused by external modulation and bringing logic elements into a defined state and separates the clock from data for facilitating introduction of information, data or commands into the electronic circuit and interpreter interprets received information or data into the electronic circuit as commands and forwards them over level shifter to the interface to operate the integrated (e.g. e-ink, LCD or rheological) display, which is also used as touch sensor.

An integrated circuit can include latched comparator circuitry. The latched comparator circuitry may include first and second input transistors configured to receive an input signal, first and second cross-coupled inverting circuits, reset transistors, and a current pulse generator. The first and second inverting circuits may each include a pull-up transistor and a pull-down transistor. The first input transistor may be coupled between the pull-up and pull-down transistors in the first inverting circuit. The second input transistor may be coupled between the pull-up and pull-down transistors in the second inverting circuit. The reset transistors may be coupled in parallel with the pull-up transistors and may receive a clock signal. The current pulse generator may receive the clock signal and generate current pulse signals in response to detecting edges in the clock signal. Latched comparator circuitry configured and operated in this way can provide reduced clock kickback noise.

A time difference amplifier (TDA) including a first delay storage unit (DSU) configured to generate a first output signal including a first transition in response to a first transition of a first input signal and a first transition of a first read signal, and a second DSU configured to generate a second output signal including a second transition in response to a second transition of a second input signal and a second transition of a second read signal. A first delay between the first and second transitions of the first and second output signals is based on a second delay between the first and second transitions of the first and second input signals and a third delay between the first and second transitions in the first and second read signals. First and second delay elements generate the first and second read signals by delaying the first and second input signals.

A Schmitt trigger voltage comparator circuit is provided including a voltage reference input, a current source having a first voltage controlled current source connected to the voltage reference input and a second voltage controlled current source connected to a signal input for converting the signal input to a input current and the voltage reference input to a reference current, a current mirror having an input connected to the output of the first voltage controlled current source configured and arranged to invert the direction of the first current and an output of the current mirror connected to the output of the second voltage controlled current source, and a sequence controller for generating digital signals to control a first plurality of switches and a second plurality of switches. The first plurality of switches control the first and second voltage controlled current sources and the second plurality of switches control the current mirror.

A synchronizer that can generate pipeline (e.g., FIFO, LIFO) status in a single step without intermediate synchronization. The status can be an indicator of whether a pipeline is full, empty, almost full, or almost empty. The synchronizer (also referred to as a double-sync or ripple-based pipeline status synchronizer) can be used with any kind of clock crossing pipeline and all kinds of pointer encodings. The double-sync and ripple-based pipeline status synchronizers eliminate costly validation and semi-manual timing closure, suggests better performance and testability, and have lower area and power.

A method for unbalancing a tri-level switching regulator uses hysteretic control when switching across multiple states of the tri-level switching regulator. The method includes determining a battery voltage and an output voltage of the tri-level switching regulator. The method also includes dynamically adjusting at least one of a first hysteretic window of a first hysteretic comparator associated with a second switching state of the tri-level switching regulator and a second hysteretic window of a second hysteretic comparator associated with a first switching state of the tri-level switching regulator based on the battery voltage and the output voltage.

A fast signal response circuit with hysteresis control includes a switch element and a comparator. The switch element includes a first and a second input terminals and a control terminal, the first terminal is configured to receive a first reference signal, the second terminal is configured to receive a second reference signal, the control terminal is configured to receive a control signal, and the switch element is configured to output the first or the second reference signal through a first output terminal according to the control signal. The comparator includes a third input terminal, a fourth input terminal and a second output terminal, the third input terminal is connected to the first output terminal, the fourth input terminal is configured to receive a sensing signal corresponding to a light input, and the second output terminal is connected to the controller and is configured to output the comparison result.

A device includes a general-purpose input/output node, a serial identifier register, and serial identifier reassignment circuitry. The serial identifier register stores a serial identifier associated with the device. The serial identifier reassignment circuitry is coupled to the general-purpose input/output node and the serial identifier register. The serial identifier reassignment circuitry sets a bit of the serial identifier based on a steady-state voltage on the general-purpose input/output node. By setting a bit of the serial identifier based on a steady-state voltage on the general-purpose input/output node, the serial identifier may be easily changed using a pull-up or pull-down resistor external to the device.

A delay independent differential hysteresis receiver. The differential hysteresis receiver uses two parallel paths in a first receiver stage, each path having a comparator with a dedicated offset on the complimentary inputs. A second receiver stage includes a hold circuit that brings the two parallel paths of the first receiver stage together to form a receiver hysteresis output.

A method for unbalancing a tri-level switching regulator uses hysteretic control when switching across multiple states of the tri-level switching regulator. The method includes determining a battery voltage and an output voltage of the tri-level switching regulator. The method also includes dynamically adjusting at least one of a first hysteretic window of a first hysteretic comparator associated with a second switching state of the tri-level switching regulator and a second hysteretic window of a second hysteretic comparator associated with a first switching state of the tri-level switching regulator based on the battery voltage and the output voltage.