A flag holding circuit includes: a flag setting part connected to a voltage supply line and charging a capacitor according to an input signal; a flag determination part outputting an output signal based on a charging voltage of the capacitor; and a discharging part discharging the capacitor. The flag setting part includes: a switch having a first terminal connected to a connection line between the flag determination part and the discharging part and a second terminal connected to the voltage supply line or a grounding line according to a signal level of the input signal, and connecting or disconnecting the voltage supply line or the grounding line with the connection line according to a leakage control signal; and a switch control part, generating the leakage control signal whose signal level changes to be greater than a power supply voltage according to a clock signal and supplying it to the switch.

A voltage reference circuit serves to furnish a reference voltage for an application-specific integrated circuit. The voltage reference circuit includes a voltage input for applying an operating voltage; a ground terminal; a voltage output for furnishing a reference voltage; and a signal output for furnishing a power-on reset signal. The voltage reference circuit includes an IPTAT circuit, connected between the voltage input and ground terminal, for generating a current proportional to the absolute temperature, the voltage reference circuit being embodied to furnish the power-on reset signal only if the reference voltage has reached a target value and if additionally a current is flowing in the IPTAT circuit with a quantity of current that reaches or exceeds a minimum current intensity determined by a voltage value of the operating voltage and by a pull-down resistance value.

An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.

A circuit includes a first inverter and a second inverter. The first inverter is coupled to an input terminal. The input terminal receives an input signal varying in a first voltage domain. The second inverter is coupled between the first inverter and an output terminal. The second inverter generating an output signal varying in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in the second voltage domain.

A semiconductor device includes a power semiconductor switch; a logic circuit connected to an input terminal; an overheat detection circuit that outputs to the logic circuit an overheat detection signal when a temperature of the power semiconductor switch exceeds an overheat detection threshold; and an overcurrent detection circuit that monitors a current that flows through the power semiconductor switch and that outputs to the logic circuit and to the overheat detection circuit an overcurrent detection signal when the current that flows through the power semiconductor switch exceeds a prescribed threshold, wherein in the overheat detection circuit, the overheat detection threshold values is changed from a first threshold value to a second threshold value that is lower than the first threshold value when the overheat detection circuit receives the overcurrent detection signal from the overcurrent detection circuit.

A discharge control circuit for a display panel includes a flip-flop configured to generate a representation of a power supply voltage of the display panel based on the power supply voltage, the representation of the power supply voltage enabling a discharge condition under which a pixel array of the display panel is discharged to be not satisfied upon power-on or during operation of the display panel and to be satisfied upon shutdown of the display panel; and a level shifter configured to level-shift timing signals for controlling operation of the pixel array, to provide the level-shifted timing signals to the display panel, and to initiate discharge of the pixel array in response to the discharge condition being satisfied.

A voltage reference circuit serves to furnish a reference voltage for an application-specific integrated circuit. The voltage reference circuit includes a voltage input for applying an operating voltage; a ground terminal; a voltage output for furnishing a reference voltage; and a signal output for furnishing a power-on reset signal. The voltage reference circuit includes an IPTAT circuit, connected between the voltage input and ground terminal, for generating a current proportional to the absolute temperature, the voltage reference circuit being embodied to furnish the power-on reset signal only if the reference voltage has reached a target value and if additionally a current is flowing in the IPTAT circuit with a quantity of current that reaches or exceeds a minimum current intensity determined by a voltage value of the operating voltage and by a pull-down resistance value.

A transmitter circuit includes a slew rate control circuit, a hysteresis circuit, a logic control circuit, and an amplifier circuit. The slew rate control circuit controls a slew rate of an input signal to generate a first output signal. The hysteresis circuit generates a first control signal according to the first output signal. The logic control circuit generates a second control signal and a third control signal according to the input signal and the first control signal. The amplifier circuit generates a second output signal according to the first output signal, the second output signal, the second control signal, and the third control signal.

One or more embodiments are directed to inter-integrated circuit (I2C) transmitters, receivers, and devices that utilize a stable reference voltage for driving a pre-driver of the transmitter and for driving a first input stage of the receiver. One embodiment is directed to a device A device that includes an inter-integrated circuit (I2C) transmitter and an I2C receiver. The I2C transmitter includes a driver coupled to an I2C data line, and a pre-driver coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver is configured to output a control signal to a control terminal of the driver. The I2C receiver includes a first stage coupled to the I2C data line, the variable first supply voltage, the second supply voltage, and the reference voltage.

A power factor corrector (PFC), such as for an on-board charger (OBC) for charging a vehicle traction battery, uses an input voltage and an input current from a power source to output a desired voltage. The PFC has an inductor and first and second power switches. A micro-controller generates, for each half-cycle of the input voltage, first and second reference signals respectively indicative of (i) a sinusoidal envelope of the inductor current for which the PFC will absorb sufficient power from the power source for the PFC to output the desired voltage and (ii) a reverse value of the inductor current for which zero voltage switching (ZVS) of the switches is ensured. A comparator assembly turns the first switch off (on) and the second switch on (off) upon the inductor current equaling the outer sinusoidal amplitude envelope (the reverse value) whereby the PFC outputs the desired voltage with ZVS.