This disclosure relates to a power supply detection circuit, including: a first input stage field effect transistor; an inverter stage; and a feedback stage field effect transistor. The inverter stage includes a complimentary pair of transistors that includes an NMOS transistor and a PMOS transistor configured and arranged such that gate lengths of the PMOS and NMOS transistors are different. The disclosure also relates to an integrated circuit including a power supply detection circuit.

A flag retaining circuit comprises a first capacitor element having one end connected to a first line and the other end grounded; a flag setting unit that charges the first capacitor element according to an input signal; a flag checking unit that outputs 0 or 1 based on the potential of the first capacitor element; and a discharging unit that discharges the first capacitor element. The discharging unit includes a transconductance element that discharges the first capacitor element via the first line; a control switch that receives supply of the voltage on a second line; and a second capacitor element having one end connected to a node between a control input end of the transconductance element and the control switch, and the other end grounded. The flag checking unit outputs the inverse of the voltage on the first line onto the second line.

This disclosure relates to systems and/or methods for subtracting in the current domain an output current primary signal from a primary sensor from an output current reference signal from a reference sensor to produce a frequency output signal indicative of the difference between the output current primary signal and the output current reference signal.

A signal conditioner for conditioning a differential oscillation signal into a compliant clock signal including first and second signal paths and a coincident gate. The first signal path toggles a first binary signal in response to the differential oscillation signal when the differential oscillation signal reaches a small amplitude level. The second signal path toggles a second binary signal in response to the differential oscillation signal only when the differential oscillation signal reaches a large amplitude level that is greater than the small amplitude level. The coincident gate toggles the clock signal high only when the first and second binary signals are both high, and toggles the clock signal low only when the first and second binary signals are both low. When the clock signal begins toggling, it may skip one or more cycles but is nonetheless compliant in terms of timing and amplitude.

A clock detector includes a first detector circuit, a second detector circuit, and a toggle detector circuit. The first detector circuit is for activating a first detect signal in response to detecting that a clock signal that toggles between first and second logic states when present is stuck in the first logic state, and keeping the first detect signal inactive otherwise. The second detector circuit is for providing a second detect signal in response to detecting that the clock signal is stuck in the second logic state, and keeping the second detect signal inactive otherwise. The toggle detector circuit is for activating a toggle detect signal in response to both the first detect signal and the second detect signal being inactive, and keeping the toggle detect signal inactive in response to an activation of either the first detect signal or the second detect signal.

A reconfigurable all-digital temperature sensor includes a NAND gate and several delay units, the NAND gate comprises two input terminals and an output terminal, one input terminal is used for external starting control signal; a plurality delay units are connected in series, the input end of the first delay unit is connected to the output terminal of the NAND gate, and the output end of the last delay unit is connected to another input terminal of the NAND gate, thereby forming a ring oscillator structure; each delay unit includes a leakage-based inverter and a Schmitt trigger, and the output end of the leakage-based inverter is connected to the input end of the Schmitt trigger. The reconfigurable all-digital temperature sensor can realize the conversion of temperature-leakage-frequency based on the ring oscillator structure in the temperature range of 40125 C., thereby reducing the design complexity and achieving high accuracy.

A power factor corrector (PFC), such as for an on-board charger (OBC) for charging a vehicle traction battery, uses an input voltage and an input current from a power source to output a desired voltage. The PFC has an inductor and first and second power switches. A micro-controller generates, for each half-cycle of the input voltage, first and second reference signals respectively indicative of (i) a sinusoidal envelope of the inductor current for which the PFC will absorb sufficient power from the power source for the PFC to output the desired voltage and (ii) a reverse value of the inductor current for which zero voltage switching (ZVS) of the switches is ensured. A comparator assembly turns the first switch off (on) and the second switch on (off) upon the inductor current equaling the outer sinusoidal amplitude envelope (the reverse value) whereby the PFC outputs the desired voltage with ZVS.

A signal conditioner for conditioning a differential oscillation signal into a compliant clock signal including first and second signal paths and a coincident gate. The first signal path toggles a first binary signal in response to the differential oscillation signal when the differential oscillation signal reaches a small amplitude level. The second signal path toggles a second binary signal in response to the differential oscillation signal only when the differential oscillation signal reaches a large amplitude level that is greater than the small amplitude level. The coincident gate toggles the clock signal high only when the first and second binary signals are both high, and toggles the clock signal low only when the first and second binary signals are both low. When the clock signal begins toggling, it may skip one or more cycles but is nonetheless compliant in terms of timing and amplitude.

A Schmitt trigger circuit includes separate circuits for monitoring change in input signal voltage level in comparison to a low threshold to generate a change in logic state of a first control signal in response to a decrease in a voltage level of the input signal and in comparison to a high threshold to generate a change in logic state of a second control signal in response to an increase in the voltage level of the input signal. A first transistor has a source-drain path connected between a supply node and an output node, with a control terminal of the first transistor configured to receive the second control signal. A second transistor has a source-drain path connected between the output node and a ground node, with a control terminal of the second transistor configured to receive said first control signal.

A circuit includes a first resistor coupled to a supply voltage node. The circuit further includes a first pair of transistors and a second pair of transistors. The first pair of transistors is coupled in series between the first resistor and an output node. The second pair of transistors is coupled in series between the output voltage node and a ground nod. A first capacitor is coupled in parallel across the first resistor.