According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrically coupled to each other, wherein the second set of transistors is configured to provide one or more output signals of the circuit, wherein the first set of transistors and the second set of transistors are electrically coupled to each other, and wherein, for each transistor of the first set of transistors and the second set of transistors, the transistor is configured to drive a load associated with the transistor and has an aspect ratio that is sized larger than an aspect ratio of a transistor that is optimized for driving the load.

The present invention provides a voltage difference measurement circuit comprising a level shifting circuit, an ADC and a calculation circuit. In the operations of the voltage difference measurement circuit, the level shifting circuit adjusts levels of a supply voltage and a ground voltage to generate an adjusted supply voltage and an adjusted ground voltage, respectively. The ADC performs an analog-to-digital converting operation upon the adjusted supply voltage and the adjusted ground voltage to generate a first digital value and a second digital value, respectively. The calculation circuit calculates a voltage difference between the supply voltage and the ground voltage according to the first digital value and the second digital value.

A power-on reset (POR) circuit includes first, second and third resistors. A first transistor has a first control terminal and first and second voltage terminals. A second transistor has a second control terminal and third and fourth voltage terminals. A third transistor has a third control terminal and fifth and sixth voltage terminals. The first control terminal is coupled via the first resistor to the second voltage terminal. The third voltage terminal is coupled via the second resistor to the first voltage terminal. The second control terminal is coupled via the third resistor to the fourth voltage terminal. The third control terminal is coupled to the third voltage terminal. The fifth voltage terminal is coupled to the first control terminal. A voltage buffer is coupled to the fifth voltage terminal.

Apparatus for generating high pulse voltage comprises a high DC voltage source, a low DC voltage source, an inductive load, two controllable gates, a controllable switch and, connected in series, a capacitor, a booster diode and an additional controllable switch, as well as a controllable pulse duration converter for pulses from a rectangular pulse generator. The preceding connection of the booster diode anode with the negative terminal of the low DC voltage source ensured by the pulse duration converter and second controllable switch correlates the booster diode switching time with the moment of closing the both controllable gates. Thus, the pulse noise present in the prior art designs is eliminated, and the level of interference emitted into the surroundings is decreased.

According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state of an enable signal, substantially pass the first clock signal to an output signal. The latch circuit may include at least two transistors configured to essentially perform a NAND function and controlled by a second clock signal, wherein the at least two transistors are configured to alter the timing of the substantial passing of the first clock signal to the output signal.

In one example, a power-on reset (POR) circuit comprises a first transistor coupled to a voltage source, a control terminal of the first transistor coupled to a non-control terminal of the first transistor via a resistor; a second transistor coupled to the resistor, a control terminal of the second transistor is coupled to a non-control terminal of the second transistor; and a comparator having first and second terminals, the first terminal coupled to the non-control terminal of the first transistor and the second terminal coupled to the voltage source via an offset circuit.

In one example, a power-on reset (POR) circuit comprises a first transistor coupled to a voltage source, a control terminal of the first transistor coupled to a non-control terminal of the first transistor via a resistor; a second transistor coupled to the resistor, a control terminal of the second transistor is coupled to a non-control terminal of the second transistor; and a comparator having first and second terminals, the first terminal coupled to the non-control terminal of the first transistor and the second terminal coupled to the voltage source via an offset circuit.

A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

A voltage clamping circuit includes a first detection circuit, a second detection circuit, and a discharge circuit. The first detection circuit detects a voltage level of a power voltage during a first operation period of a semiconductor apparatus. The second detection circuit detects the voltage level of the power voltage during a second operation period of the semiconductor apparatus. The discharge circuit changes the voltage level of the power voltage based on the detection results of the first and second detection circuits.