A level shifter includes a first output terminal and a second output terminal. After an output signal in a high level state is outputted from the first output terminal and an inverted output signal in a low level state is outputted from the second output terminal, a weak driving circuit is connected between the first output terminal and a power supply voltage, and a strong driving circuit is connected between the second output terminal and the power supply voltage. After the output signal in the low level state is outputted from the first output terminal and the inverted output signal in the high level state is outputted from the second output terminal, the strong driving circuit is connected between the first output terminal and the power supply voltage, and the weak driving circuit is connected between the second output terminal and the power supply voltage.

An isolated switched-mode power converter converts power from an input source into power for an output load. A digital controller senses a secondary-side voltage, such as a rectified voltage, of the power converter. The secondary-side voltage is divided down using a high-impedance voltage divider. The resultant divided-down voltage is provided to a voltage sensor within the digital controller. The voltage sensor level shifts the provided voltage, and buffers the resulting level-shifted voltage. The buffered, level-shifted voltage is provided to a tracking analog-to-digital converter (ADC) for digitization. The buffered signal provided to the tracking ADC has a high current capability, such that the voltage input to the tracking ADC may quickly converge before the tracking ADC outputs a digital value for the sensed secondary-side voltage.

A driver shutdown circuit configured to trigger driver shutdown based on the magnitude and duration of the driving current. A first GaN FET is connected to a second GaN FET and an input node and generates a discharging current proportional to the driving current. The discharging current is drawn from a timer capacitor through the first and second GaN FETs. The second GaN FET receives a control signal and stops flow of the discharging current in between driver pulses so a pre-charger circuit can recharge the timer capacitor to a particular voltage. The discharging current drains the timer capacitor, and a shutdown signal generator outputs a shutdown signal to the driver in response to the voltage on the timer capacitor decreasing below a triggering voltage.

An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.

An ion trap apparatus (e.g., ion trap chip) having a plurality of electrodes is provided. The ion trap apparatus may comprise a plurality of interconnect layers, a substrate, and at least one integrated switching network layer disposed between the plurality of interconnect layers and the substrate. The integrated switching network layer may comprise a plurality of monolithically-integrated controls and/or switches configured to condition a voltage signal applied to at least one of the plurality of electrodes. An example ion trap apparatus may comprise a surface ion trap chip. The ion trap apparatus may be configured to operate within a cryogenic chamber.

Embodiments described herein provide a dual-line FIFO structure without the use of any multiplexer. Instead, the dual-line FIFO described herein uses a selectively transparent latch and a flip-flop serially connected to the latch, such that the combination of the serially connected latch and the flip-flop can temporarily store up to two data units at two clock cycles.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.

A driver shutdown circuit configured to trigger driver shutdown based on the magnitude and duration of the driving current. A first GaN FET is connected to a second GaN FET and an input node and generates a discharging current proportional to the driving current. The discharging current is drawn from a timer capacitor through the first and second GaN FETs. The second GaN FET receives a control signal and stops flow of the discharging current in between driver pulses so a pre-charger circuit can recharge the timer capacitor to a particular voltage. The discharging current drains the timer capacitor, and a shutdown signal generator outputs a shutdown signal to the driver in response to the voltage on the timer capacitor decreasing below a triggering voltage.

The present disclosure relates to a comparator, an AD converter, a solid-state image pickup device, an electronic device, a method of controlling the comparator, a data writing circuit, a data reading circuit, and a data transferring circuit, capable of improving the determining speed of the comparator and reducing power consumption. The comparator includes a differential input circuit configured to operate with a first power supply voltage, the differential input circuit configured to output a signal when an input signal is higher than a reference signal in voltage; a positive feedback circuit configured to operate with a second power supply voltage lower than the first power supply voltage, the positive feedback circuit being configured to accelerate transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal of the differential input circuit; and a voltage conversion circuit configured to convert the output signal of the differential input circuit into a signal corresponding to the second power supply voltage. The present disclosure can be applied to, for example, a comparator of a solid-state image pickup device.