A trigger, includes: a first voltage input terminal; a bias voltage input terminal; a first bias transistor having a scaling of N to a first component of an external device; a comparator transistor having a scaling of N to a second component of the external device; a first switch transistor and a second switch transistor; a shunt transistor having a control terminal connected to the first voltage input terminal, a second terminal connected to the second terminal of the second switch transistor, and a first terminal connected to the first terminal of the comparator transistor. The shunt transistor has an enlarging scale of M to the comparator transistor. A voltage output terminal is respectively connected to the second terminal of the first switch transistor, the control terminal of the second switch transistor, and the second terminal of the comparator transistor.

Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.

Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.

An integrated circuit (“IC”) includes an input receiver with multiple hysteresis levels. An exemplary input receiver may be an input buffer with a Schmitt trigger that has multiple hysteresis windows between different high and low input voltages. This circuit may improve the input noise immunity of the external input signals and timing by allowing for a selection one of the plurality of levels depending on parameters of the input (e.g. noise level).

An integrated circuit (“IC”) includes an input receiver with multiple hysteresis levels. An exemplary input receiver may be an input buffer with a Schmitt trigger that has multiple hysteresis windows between different high and low input voltages. This circuit may improve the input noise immunity of the external input signals and timing by allowing for a selection one of the plurality of levels depending on parameters of the input (e.g. noise level).

A semiconductor apparatus includes a control circuit and a level shifter. The control circuit is configured to output a power control signal for activating a data input/output circuit operated by a first voltage when the first voltage is higher than a first set voltage and a second voltage is higher a second set voltage. The level shifter configured to receive the power control signal and lower operating voltages of devices including a plurality of transistors with a thin gate insulating layer based on the power control signal.

A semiconductor apparatus includes a control circuit and a level shifter. The control circuit is configured to output a power control signal for activating a data input/output circuit operated by a first voltage when the first voltage is higher than a first set voltage and a second voltage is higher a second set voltage. The level shifter configured to receive the power control signal and lower operating voltages of devices including a plurality of transistors with a thin gate insulating layer based on the power control signal.

A hysteresis comparator that has a small circuit area and low power consumption is provided. A differential pair in the comparator is formed using transistors each including a back gate. The comparator is configured to apply an inverted signal of a logic value of an output signal of the comparator to the back gate of the transistor. That is, the threshold voltage of the transistor is controlled by the inverted signal. By the change of the threshold voltage, hysteresis can be added to an input comparison voltage.

A circuit for comparing a voltage with a threshold, including: first and second nodes of application of the voltage; a first branch including a first transistor series-connected with a first resistor between first and second nodes; a second branch parallel to the first branch, including second and third series-connected resistors forming a voltage dividing bridge between the first and second nodes, the midpoint of the dividing bridge being connected to a control node of the first transistor; and a third branch including a second transistor in series with a resistive and/or capacitive element, between the control node of the first transistor and the first or second node, a control node of the second transistor being connected to the junction point of the first transistor and of the first resistor.

A circuit for comparing a voltage with a threshold, including: first and second nodes of application of the voltage; a first branch including a first transistor series-connected with a first resistor between first and second nodes; a second branch parallel to the first branch, including second and third series-connected resistors forming a voltage dividing bridge between the first and second nodes, the midpoint of the dividing bridge being connected to a control node of the first transistor; and a third branch including a second transistor in series with a resistive and/or capacitive element, between the control node of the first transistor and the first or second node, a control node of the second transistor being connected to the junction point of the first transistor and of the first resistor.