A device includes a sensor and an oscillator. The sensor provides a temperature-sensitive voltage. The oscillator includes a digital delay cell and an adjustment device. The adjustment device, based on the temperature-sensitive voltage, adjusts a delay of the digital delay cell, wherein the digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.

There are provided an oscillator and a memory system including the same. In the oscillator including an odd number of inverters sequentially coupled, in which an output signal of an inverter of a last stage is fed back as an input signal of an inverter of a first stage, wherein each of the inverters includes: a first input signal control unit configured to delay an input signal of each of the inverters by a first delay time or a second delay time and output a first delay input signal; a second input signal control unit configured to delay the input signal by a third delay time or a fourth delay time and output a second delay input signal; and a signal output unit configured to an output signal in response to the first delay input signal and the second delay input signal.

Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.

Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.

Current-starving in tunable-length delay (TLD) circuits in adaptive clock distribution (ACD) systems for compensating voltage droops in clocked integrated circuits (ICs) is disclosed. Voltage droops slow propagation of signals in clocked circuits. However, clock delay circuits in a TLD circuit increase a clock period by increasing a clock delay in response to a voltage droop. In large power distribution networks (PDN), impedance can delay and reduce the magnitude of voltage droops experienced at the TLD circuit. If the voltage droop at the TLD circuit is smaller than at the clocked circuit, then the clock period isn't stretched enough to compensate the slowed clocked circuit. A current-starved TLD circuit starves the clock delay circuits of current in response to a voltage droop indication, which further increases the clock signal delay, and further stretches the clock period to overcome a larger voltage droop in clocked circuits in other areas of the IC.

An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.

There are provided an oscillator and a memory system including the same. In the oscillator including an odd number of inverters sequentially coupled, in which an output signal of an inverter of a last stage is fed back as an input signal of an inverter of a first stage, wherein each of the inverters includes: a first input signal control unit configured to delay an input signal of each of the inverters by a first delay time or a second delay time and output a first delay input signal; a second input signal control unit configured to delay the input signal by a third delay time or a fourth delay time and output a second delay input signal; and a signal output unit configured to an output signal in response to the first delay input signal and the second delay input signal.

Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.

A semiconductor module including a semiconductor element, a controller, a cooler, and a temperature sensor are included. The controller is connected to the semiconductor module and controls switching operation of the semiconductor element. The temperature sensor measures a coolant temperature, which is a temperature of the coolant. The controller controls turn-off speed of the semiconductor element based on the coolant temperature. The controller increases the turn-off speed as the coolant temperature rises.