An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.

Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to include circuitry that exhibits both proportional to absolute temperature (PTAT) characteristics and complementary to absolute temperature (CTAT) characteristics in order to control delay times across a range of operating temperatures. The RC delay circuits may include a first type of circuitry having impedance with PTAT characteristics that is coupled to an output node in parallel with a second type of circuitry having impedance with CTAT characteristics. The first type of circuitry may include a resistor and the second type of circuitry may include a transistor, in some embodiments.

A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.

An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.

The disclosure provides a delay line circuit including an output stage. The output stage includes a first inverter cell, a second inverter cell, a correction circuit, and a first switch capacitor array. The input terminal of the first inverter cell receives a reference clock signal. The input terminal of the second inverter cell is coupled with the output terminal of the first inverter cell. The first terminal of the correction circuit is coupled with the output terminal of the first inverter cell, and the second terminal of the correction circuit is coupled with a ground, wherein the correction circuit corrects a duty cycle of the delay line circuit. The first terminal of the first switch capacitor array is coupled with the output terminal of the second inverter cell, and the second terminal of the first switch capacitor array is coupled with the ground.

Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.

An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.

Exemplary embodiments may include a method of applying a charging pulse to an output capacitor, detecting satisfaction of a charging threshold, ending the charging pulse in response to the detecting the satisfaction of the charging threshold, and discharging the sampling capacitor in response to the detecting the satisfaction of the charging threshold. In some embodiments, once a sampling capacitor voltage drops below a discharging threshold, a charging pulse is applied. Exemplary embodiments may also include an apparatus with a controller coupled to an input node, a timer coupled to the controller, an inductive charger coupled to the controller, to an input node, and to an output node, and a sensor coupled to the controller and the output node. Exemplary embodiments may further include an apparatus where a sensor with a sampling capacitor has a first terminal coupled to the output node and a second terminal coupled to the controller and the inductive charger.