A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.

An integrated circuit delay cell includes an input circuit to establish a current level in the circuit, a switch configured to control an on/off time of a delay circuit, a delay circuit including at least one current starved stage configured to mirror the current level, the delay circuit configured to control a speed of a rise and/or fall time of an output signal, and a glitch discharging circuit connected to the delay circuit configured to tolerate and discharge unwanted charge of the delay circuit.

An integrated circuit delay cell includes an input circuit to establish a current level in the circuit, a switch configured to control an on/off time of a delay circuit, a delay circuit including at least one current starved stage configured to mirror the current level, the delay circuit configured to control a speed of a rise and/or fall time of an output signal, and a glitch discharging circuit connected to the delay circuit configured to tolerate and discharge unwanted charge of the delay circuit.

Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to include circuitry that exhibits both proportional to absolute temperature (PTAT) characteristics and complementary to absolute temperature (CTAT) characteristics in order to control delay times across a range of operating temperatures. The RC delay circuits may include a first type of circuitry having impedance with PTAT characteristics that is coupled to an output node in parallel with a second type of circuitry having impedance with CTAT characteristics. The first type of circuitry may include a resistor and the second type of circuitry may include a transistor, in some embodiments.

The method is used for transmitting signals and data within at least one first and one second transmission phase (TP1, TP2), which follow one another synchronously or asynchronously, between a first communication unit (L) and at least one second communication unit (Z), which comprises a central processor unit (CPU), a memory unit (M), in which an operating program (OP) is stored, and at least one first event generator (EG1), which monitors signal sequences (SL, SZ) transmitted via a transmission line (W) between the two communication units (L, Z) independently of the central processor unit (CPU) and generates event notifications (e1, e2) for events during the data transmission, which occur in accordance with the applied transmission protocol, which event notifications are transmitted to the central processor unit (CPU) and/or to at least one event user (EU1).

An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.

A temperature-compensated ring oscillator circuit includes a plurality of series-coupled inverters in a ring configuration and a plurality of capacitors. Each capacitor couples to an output of a corresponding inverter. A first transistor is included that comprises a first control input and first and second current terminals. The second current terminal couples to the power supply terminal of each inverter. A second transistor is included that comprises a second control input and third and fourth current terminals. A resistor couples to the fourth current terminal of the second transistor at a first node. An amplifier includes a first amplifier input, a second amplifier input, and an amplifier output. The amplifier output couples to the first and second control inputs. The first amplifier input couples to the second current terminal of the first transistor and the second amplifier input couples to the first node.

The slew rate control circuit includes a slew rate control unit, a capacitive delay unit, a delay unit, a first output unit, a second output unit, and a third output unit. The slew rate control unit is used for receiving a plurality of control voltages. The capacitive delay unit is coupled to the slew rate control unit for receiving an input signal. The delay unit is coupled to the capacitive delay unit. The first output unit and the second output unit are coupled to the capacitive delay unit. The third output unit is coupled to the delay unit. The first output signal and the second output signal are two signals without controllable slew rates. A slew rate of the third output signal is controlled by the capacitive delay unit. A slew rate of the fourth output signal is controlled by the capacitive delay unit and the delay unit.

An embodiment circuit includes a first voltage-controlled delay line (VCDL), a second VCDL, and a first flip-flop. The first VCDL includes a first input terminal configured to receive a first input voltage, and a second input terminal configured to receive a clock signal. The second VCDL includes a first input terminal configured to receive a second input voltage, and a second input terminal configured to receive the clock signal. The first flip-flop includes a reset pin coupled to an output terminal of the first VCDL, and a clock pin coupled to an output terminal of the second VCDL.