The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.

A circuit comprises a cycle-cycle detector, configured to receive a synthesized clock signal, and detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals; a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; and a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector; wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal.

A synchronous circuit may be provided. The synchronous circuit may include a first buffer configured to receive an input signal and control the transition timing of an output signal based on a control code. The synchronous circuit may include a delay circuit configured to control a delay time based on the control code to constantly maintain a time that the input signal received by the first buffer arrives at a synchronizing circuit.

A synchronous circuit may be provided. The synchronous circuit may include a first buffer configured to receive an input signal and control the transition timing of an output signal based on a control code. The synchronous circuit may include a delay circuit configured to control a delay time based on the control code to constantly maintain a time that the input signal received by the first buffer arrives at a synchronizing circuit.

A circuit comprises a cycle-cycle detector, configured to receive a synthesized clock signal, and detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals; a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; and a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector; wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal.

A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.

A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.

An example clock delivery system includes a phase-locked loop (PLL) configured to generate a plurality of input clocks, a phase interpolator configured to receive the plurality of input clocks and generate a plurality of output clocks, and a clock data recovery (CDR) circuit configured to receive the plurality of output clocks. The phase interpolator includes a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to output thermometer codes, and a mixer circuitry segmented into a plurality of unit circuits that are enabled or disabled based on bits of the thermometer codes.

A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.