The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. The driver circuit includes a variable load arranged for outputting the second signal by adding delay to the first signal. The delay control circuit also includes a control circuit arranged to receive the first signal and to control the variable load of the driver circuit based on a current state of the first signal and on a control signal indicative of an amount of delay to be added to the first signal in the current state.

An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.

A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.

A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.

In some examples, a circuit is described. The circuit may be included in a digital phase-locked loop (PLL) and may include a first delay cell, a second delay cell, and a delay controller. The first delay cell may include a first inverter circuit that includes first and second transistors and may be configured to receive and to delay a first signal. The delay of the first inverter circuit may be based on first and second voltages respectively provided to the first and second transistors. The second delay cell may include a second inverter circuit that includes third and fourth transistors and may be configured to receive and to delay a second signal. The delay of the second inverter circuit may be based on third and fourth voltages respectively provided to the third and fourth transistors. The delay controller may be configured to provide the first, second, third, and fourth voltages.

A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.

A delay adjustment circuit according to an embodiment includes: a plurality of delay adjustment units connected in series, each of the plurality of delay adjustment units including one or more first delay elements (102) connected in series that delay an input signal on the basis of a clock, and a first selector (120) that outputs one of the input signal and an output of the first delay element at a last stage among the one or more first delay elements; and an output unit (103, 104, 130a, 130b, 140) that outputs a clock according to an output of the first selector included in a delay adjustment unit at a last stage among the plurality of delay adjustment units, in which each of the plurality of delay adjustment units includes a different number of the first delay elements.

According to one implementation, a circuit includes a first digital gate (108A) and a timing offset circuit portion (238) coupled to the first digital gate (108A) that includes one or more tri-state inverters (202A . . . 202N) where a capacitance at an output of the first digital gate (108A) is based on a quantity of enabled tri-state inverters of the one or more tri-state inverters (202A-202N).