A phase interpolating (PI) system includes: a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal, the PI stage being further configured to avoid a pull-up/pull-down (PUPD) short-circuit situation by using the multi-bit weighting signal and a logical inverse thereof (multi-bit weighting_bar signal); and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component; the capacitive component being tunable; and the capacitive component having a Miller effect configuration resulting in a reduced footprint of the amplifying stage.

Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

In an embodiment an oscillator device includes a ring oscillator circuit with at least one delay stage with an output of a last delay stage fed back to an input of a first delay stage, wherein each of the delay stages is configured to receive a charging current and to provide a delay that is dependent on the charging current and at least one of the delay stages includes a metal-oxide-semiconductor field-effect transistor and a bias circuit including an output terminal coupled to an input terminal of the ring oscillator circuit, wherein the bias circuit is configured to receive a temperature-independent reference voltage and includes a current source with a main NMOS-transistor, the current source configured to provide a control current to the ring oscillator circuit which is proportional to a difference of the temperature-independent reference voltage and a gate-source voltage of the main NMOS-transistor, and wherein the gate-source voltage of the main NMOS-transistor includes a negative temperature coefficient.

Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

A phase interpolating (PI) system includes: a PI stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component. The capacitive component is tunable to exhibit non-zero capacitances. The capacitive component has a Miller effect configuration resulting in a reduced footprint of the amplifying stage.

In an embodiment an oscillator device includes a ring oscillator circuit with at least one delay stage with an output of a last delay stage fed back to an input of a first delay stage, wherein each of the delay stages is configured to receive a charging current and to provide a delay that is dependent on the charging current and at least one of the delay stages includes a metal-oxide-semiconductor field-effect transistor and a bias circuit including an output terminal coupled to an input terminal of the ring oscillator circuit, wherein the bias circuit is configured to receive a temperature-independent reference voltage and includes a current source with a main NMOS-transistor, the current source configured to provide a control current to the ring oscillator circuit which is proportional to a difference of the temperature-independent reference voltage and a gate-source voltage of the main NMOS-transistor, and wherein the gate-source voltage of the main NMOS-transistor includes a negative temperature coefficient.

Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

A gated tri-state (G3S) inverter includes: first, second and third transistors of a first dopant type (D1 transistors) and first, second and third transistors of a second dopant type (D2 transistors) serially connected between a first reference voltage and second reference voltage, the second dopant type being different than the first dopant type; gate terminals of an alpha one of the noted D1 transistors and an alpha one of the noted D2 transistors being configured to receive an input signal; gate terminals of a beta one of the noted D1 transistors and a beta one of the noted D2 transistors being configured to receive a gating signal; a gate terminal of a gamma one of the noted D2 transistors being configured to receive an enable signal; and a gate terminal of a gamma one of the noted D1 transistors being configured to receive an enable_bar signal.

Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.

A gated tri-state (G3S) inverter includes: first, second and third transistors of a first dopant type (D1 transistors) and first, second and third transistors of a second dopant type (D2 transistors) serially connected between a first reference voltage and second reference voltage, the second dopant type being different than the first dopant type; gate terminals of an alpha one of the noted D1 transistors and an alpha one of the noted D2 transistors being configured to receive an input signal; gate terminals of a beta one of the noted D1 transistors and a beta one of the noted D2 transistors being configured to receive a gating signal; a gate terminal of a gamma one of the noted D2 transistors being configured to receive an enable signal; and a gate terminal of a gamma one of the noted D1 transistors being configured to receive an enable_bar signal.